PIC24F32KA301-E/SO Microchip Technology, PIC24F32KA301-E/SO Datasheet - Page 223
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PIC24F32KA301-E/SO
Manufacturer Part Number
PIC24F32KA301-E/SO
Description
32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 20 SOIC .300in
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.PIC24F16KA301T-ISO.pdf
(320 pages)
Specifications of PIC24F32KA301-E/SO
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (0.295", 7.50mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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22.2
The analog input model of the 12-bit A/D Converter is
shown in
A/D is a function of the holding capacitor charge time.
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the voltage level on the analog input
pin. The source impedance (R
impedance (R
(R
required to charge C
the analog sources must, therefore, be small enough to
fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage
currents on the accuracy of the A/D Converter, the
maximum recommended source impedance, R
2.5 k. After the analog input channel is selected
(changed), this sampling function must be completed
FIGURE 22-2:
2011 Microchip Technology Inc.
SS
) impedance combine to directly affect the time
A/D Sampling Requirements
Figure
Note: C
IC
) and the internal sampling switch
22-2. The total sampling time for the
PIN
VA
HOLD
value depends on device package and is not tested. Effect of C
Rs
12-BIT A/D CONVERTER ANALOG INPUT MODEL
. The combined impedance of
ANx
C
PIN
Legend: C
HOLD
S
), the interconnect
) must be allowed
V
I
R
R
C
LEAKAGE
T
PIN
IC
SS
HOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample-and-Hold Capacitance (from DAC)
S
PIC24FV32KA304 FAMILY
various junctions
, is
R
I
500 nA
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
At least 1 T
conversions for the sample time. For more details, see
Section 29.0 “Electrical
EQUATION 22-1:
LEAKAGE
IC
Note:
250
AD
Based on T
and PLL are disabled.
PIN
Sampling
time period should be allowed between
T
Switch
ADCS
AD
negligible if Rs 5 k.
R
=
SS
T
A/D CONVERSION CLOCK
PERIOD
=
CY
CY
T
--------- - 1
T
R
Characteristics”.
AD
CY
SS
ADCS
= 2/F
V
3 k
–
SS
C
= 4.4 pF
HOLD
OSC
+
DS39995B-page 223
1
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