PIC24FJ16MC101-I/P Microchip Technology, PIC24FJ16MC101-I/P Datasheet - Page 67
![16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 20 PDIP .300in TUBE](/photos/40/66/406676/20-dip_sml.jpg)
PIC24FJ16MC101-I/P
Manufacturer Part Number
PIC24FJ16MC101-I/P
Description
16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheet
1.PIC24FJ16MC101-IP.pdf
(304 pages)
Specifications of PIC24FJ16MC101-I/P
Featured Product
PIC24FJ/33FJ MCUs & dsPIC® DSCs
Core Processor
PIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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REGISTER 7-1:
REGISTER 7-2:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 7-5
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
0’ = Bit is cleared
bit 3
Note 1:
R/W-0
IPL2
U-0
U-0
U-0
—
—
—
2:
3:
2:
(2)
(3)
For complete register details, see
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
For complete register details, see
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
R/W-0
IPL1
U-0
U-0
U-0
—
—
—
SR: CPU STATUS REGISTER
CORCON: CORE CONTROL REGISTER
(2)
(3)
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R/W-0
IPL0
U-0
U-0
U-0
—
—
—
(2)
(3)
Register 3-1: “SR: CPU Status
Register 3-2: “CORCON: Core Control
U-0
R-0
U-0
U-0
RA
Preliminary
—
—
—
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
-n = Value at POR
U = Unimplemented bit, read as ‘0’
(2)
IPL3
R/W-0
R/C-0
U-0
U-0
—
—
N
(2)
(2)
(1)
PIC24FJ16MC101/102
R/W-0
R/W-0
Register”.
PSV
U-0
U-0
OV
—
—
Register”.
‘1’ = Bit is set
R/W-0
U-0
U-0
U-0
—
—
—
Z
DS39997B-page 67
R/W-0
R/W-0
U-0
U-0
DC
—
—
C
bit 8
bit 0
bit 8
bit 0
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