PIC24FJ48GA004-I/ML Microchip Technology, PIC24FJ48GA004-I/ML Datasheet - Page 143

• Manufacturer Part Number: PIC24FJ48GA004-I/ML
• Description: 16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ48GA004-I/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 15-2:
 2010 Microchip Technology Inc.
SSx/FSYNCx
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 1.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
SDOx
SCKx
SDIx
Clear the SPIxIF bit in the respective IFSx
register.
Set the SPIxIE bit in the respective IECx
register.
Write the SPIxIP bits in the respective IPCx
register.
Read SPIxBUF
Control
registers
Transfer
Sync
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Receive Buffer
8-Level FIFO
bit0
with
SPIxSR
Control
SPIxBUF
Clock
Shift Control
Transmit Buffer
8-Level FIFO
MSTEN
PIC24FJ64GA004 FAMILY
Transfer
Write SPIxBUF
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPIxBUF register.
If using interrupts:
• Clear the SPIxIF bit in the respective IFSx
• Set the SPIxIE bit in the respective IECx
• Write the SPIxIP bits in the respective IPCx
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
register.
register.
register to set the interrupt priority.
Secondary
Prescaler
1:1 to 1:8
Internal Data Bus
registers
1:1/4/16/64
Prescaler
Primary
with
DS39881D-page 143
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
F
CY
MSTEN