PIC24FJ48GA004T-I/ML Microchip Technology, PIC24FJ48GA004T-I/ML Datasheet - Page 14
![16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24FJ48GA004T-I/ML
Manufacturer Part Number
PIC24FJ48GA004T-I/ML
Description
16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ48GA004T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC24FJXXXGA0XX
3.2.2
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register, out of the device,
over the PGDx pin. After the REGOUT control code is
received, the CPU is held Idle for 8 cycles. After these
8 cycles, an additional 16 cycles are required to clock the
data out (see Figure 3-3).
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
FIGURE 3-3:
DS39768D-page 14
PGCx
PGDx
Fetch REGOUT Control Code
Execute Previous Instruction, CPU Held in Idle
REGOUT SERIAL INSTRUCTION
EXECUTION
1
1
0
2
PGDx = Input
0
3
REGOUT SERIAL EXECUTION
0
4
P4
1
2
7
8
P5
LSb
1
1
2
2
3
3
4
Shift Out VISI Register<15:0>
4
5
PGDx = Output
...
Note 1: After the contents of VISI are shifted out,
6
10
11
2: Data changes on the falling edge and
11
12
the
maintains PGDx as an output until the
first rising edge of the next clock is
received.
latches on the rising edge of PGCx. For
all
Significant bit (LSb) is transmitted first.
12
13
13
14
data
14
PIC24FJXXXGA0XX
15 16
MSb
© 2008 Microchip Technology Inc.
transmissions,
P4A
0
No Execution Takes Place,
Fetch Next Control Code
1
PGDx = Input
0
2
0
3
the
0
4
device
Least