PIC24HJ128GP502-H/SO Microchip Technology, PIC24HJ128GP502-H/SO Datasheet - Page 4
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PIC24HJ128GP502-H/SO
Manufacturer Part Number
PIC24HJ128GP502-H/SO
Description
16-bit MCU, 128KB Flash, CAN, DMA, 40 MIPS, NanoWatt 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ128GP502-H/SO
Core Processor
PIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (43K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Silicon Errata Issues
1. Module: UART
2. Module: UART
DS80441F-page 4
Note:
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
Affected Silicon Revisions
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
A1
A1
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A2
A2
X
X
A3
A3
X
X
A4
A4
X
X
3. Module: SPI
4. Module: SPI
The SPI Transmit Buffer Full (SPITBF) flag does
not get set immediately after writing to the buffer.
Work around
After a write to the SPI buffer, poll the SPITBF flag
until the flag gets set, indicating that the transmit
buffer is not full. Afterwards, poll the SPITBF flag
again until the flag gets cleared, indicating that the
transmit has started and that the transmit buffer is
empty and another write can occur.
Affected Silicon Revisions
The SPI module will generate incorrect frame
synchronization pulses when configured in Frame
Master mode if the start of data is selected to
coincide with the start of the frame synchronization
pulse (FRMEN = 1, SPIFSD = 0, FRMDLY = 1).
However, the module functions correctly in Frame
Slave mode, and also in Frame Master mode if
FRMDLY = 0.
Work around
If DMA is not being used, manually drive the SSx
pin (x = 1 or 2) high using the associated PORT
register, and then drive it low after the required 1
bit-time pulse width. This operation needs to be
performed when the transmit buffer is written.
If DMA is being used, and if no other peripheral
modules are using DMA transfers, use a timer
interrupt to periodically generate the frame
synchronization
described above) after every 8 or 16-bit periods
(depending on the data word size, configured
using the MODE16 bit).
If FRMDLY = 0, no work around is needed.
Affected Silicon Revisions
A1
A1
X
X
A2
A2
X
X
A3
A3
X
X
pulse
© 2010 Microchip Technology Inc.
A4
A4
X
X
(using
the
method