PIC24HJ128GP504-H/PT Microchip Technology, PIC24HJ128GP504-H/PT Datasheet - Page 73

• Manufacturer Part Number: PIC24HJ128GP504-H/PT
• Description: 16-bit MCU, 128KB Flash, CAN, DMA, 40 MIPS, NanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ128GP504-H/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (43K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 7-3:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NSTDIS
R/W-0
U-0
—
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
Unimplemented: Read as ‘0’
DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divide by zero
0 = Math error trap was not caused by a divide by zero
DMACERR: DMA Controller Error Status bit
1 = DMA controller error trap has occurred
0 = DMA controller error trap has not occurred
MATHERR: Arithmetic Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
DIV0ERR
R/W-0
U-0
—
INTCON1: INTERRUPT CONTROL REGISTER 1
‘1’ = Bit is set
W = Writable bit
DMACERR
R/W-0
U-0
—
MATHERR
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADDRERR
R/W-0
U-0
—
STKERR
R/W-0
U-0
—
x = Bit is unknown
OSCFAIL
R/W-0
U-0
—
DS70293E-page 73
U-0
U-0
—
—
bit 8
bit 0