PIC24HJ12GP202-E/SO Microchip Technology, PIC24HJ12GP202-E/SO Datasheet - Page 3

• Manufacturer Part Number: PIC24HJ12GP202-E/SO
• Description: 12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP202-E/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
UART
CPU
ADC
SPI
I
I
I
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Consumption
Addressing
Generation
Instruction
Character
FRMDLY
SILICON ISSUE SUMMARY (CONTINUED)
Feature
in Sleep
Current
Break
10-bit
Slave
Mode
EXCH
—
—
Number
Item
19.
20.
21.
22.
23.
24.
25.
With the I
interrupt input functions (if any) associated with SCL and
SDA pins do not reflect the actual digital logic levels on the
pins.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit
reserved addresses.
After the ACKSTAT bit is set when receiving a NACK, it
may be cleared by the reception of a Start or Stop bit.
The EXCH instruction does not execute correctly.
The UART module will not generate back-to-back Break
characters.
The SPI communication in Framed mode does not function
correctly if the Slave SPI frame delay bit (FRMDLY) is set
to ‘1’.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
2
C module enabled, the port bits and external
Issue Summary
PD
) of the
A2 A3 A4 A5
X
X
X
X
X
X
X
DS80466E-page 3
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X