PIC24HJ16GP304T-I/ML Microchip Technology, PIC24HJ16GP304T-I/ML Datasheet - Page 41
![16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24HJ16GP304T-I/ML
Manufacturer Part Number
PIC24HJ16GP304T-I/ML
Description
16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
Specifications of PIC24HJ16GP304T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24HJ16GP304T-I/MLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ16GP304T-I/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- Current page: 41 of 272
- Download datasheet (4Mb)
TABLE 4-23:
4.3.3
Move instructions provide a greater degree of
addressing flexibility than the other instructions. In
addition to the Addressing modes supported by most
MCU instructions, MOV instructions also support
Register Indirect with Register Offset Addressing
mode. This is also referred to as Register Indexed
mode.
In summary, move instructions support the following
addressing modes:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
4.3.4
Besides the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
© 2011 Microchip Technology Inc.
File Register Direct
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset
(Register Indexed)
Register Indirect with Literal Offset
Note:
Note:
Addressing Mode
PIC24HJ32GP202/204 AND PIC24HJ16GP304
MOVE (MOV) INSTRUCTION
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and the destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
OTHER INSTRUCTIONS
FUNDAMENTAL ADDRESSING MODES SUPPORTED
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the Effective Address (EA.)
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
The sum of Wn and Wb forms the EA.
The sum of Wn and a literal forms the EA.
Description
DS70289G-page 41
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