PIC24HJ32GP204-E/ML Microchip Technology, PIC24HJ32GP204-E/ML Datasheet - Page 6

• Manufacturer Part Number: PIC24HJ32GP204-E/ML
• Description: 16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP204-E/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24HJ32GP202/204 and PIC24HJ16GP304
13. Module: UART
14. Module: Internal Voltage Regulator
15. Module: PSV Operations
DS80467E-page 6
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
When the VREGS bit (RCON<8>) is set to a logic
‘0’, device may Reset and higher sleep current
may be observed.
Work around
Ensure VREGS bit (RCON<8>) is set to a logic ‘1’
for device Sleep mode operation.
Affected Silicon Revisions
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
A2
A2
A2
X
X
mode) with pre/post-decrement
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
A5
A5
A5
X
X
X
A6
A6
A6
X
X
X
16. Module: I
17. Module: I
18. Module: I
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
With the I
external
associated with the SCL and SDA pins do not
reflect the actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
in order to be read correctly. This issue does not
affect the operation of the I
Affected Silicon Revisions
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register I2CxRCV, if the lower address
byte
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
A2
A2
A2
X
X
X
matches
A3
A3
A3
X
X
X
than
2
interrupt
C module enabled, the PORT bits and
2
2
2
2
C
C
C
C module is configured as a 10-bit
A4
A4
A4
X
X
X
0x02;
the
© 2010 Microchip Technology Inc.
A5
A5
A5
X
X
X
input
reserved
however,
A6
A6
A6
2
X
X
X
C module.
functions
addresses.
the
(if
module
any)
In