PIC24HJ64GP204-E/ML Microchip Technology, PIC24HJ64GP204-E/ML Datasheet - Page 71
![16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24HJ64GP204-E/ML
Manufacturer Part Number
PIC24HJ64GP204-E/ML
Description
16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ64GP204-E/ML
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP204-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC24HJ64GP204-E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- Current page: 71 of 368
- Download datasheet (5Mb)
7.3
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and
PIC24HJ128GPX02/X04 devices implement a total of
30 registers for the interrupt controller:
• INTCON1
• INTCON2
• IFSx
• IECx
• IPCx
• INTTREG
7.3.1
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
© 2011 Microchip Technology Inc.
Interrupt Control and Status
Registers
INTCON1 AND INTCON2
IFSx
IECx
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
7.3.4
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.3.5
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
7.3.6
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS register, SR, contains the
• The CORCON register contains the IPL3 bit
All Interrupt registers are described in
through
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user
software can change the current CPU priority
level by writing to the IPL bits.
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
Register
Table
IPCx
INTTREG
STATUS/CONTROL REGISTERS
7-1. For example, the INT0 (External
7-29.
DS70293E-page 71
Register 7-1
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