PIC32MX110F016B-I/SS Microchip Technology, PIC32MX110F016B-I/SS Datasheet - Page 308

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PIC32MX110F016B-I/SS

Manufacturer Part Number
PIC32MX110F016B-I/SS
Description
PIC32, 16KB Flash, 4KB RAM, 40 MHz, CTMU, 4 DMA 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Datasheet
PIC32MX1XX/2XX
TABLE A-1:
DS61168C-page 308
4.0 “Memory Organization”
8.0 “Oscillator Configuration”
21.0 “10-bit Analog-to-Digital
Converter (ADC)”
24.0 “Charge Time Measurement
Unit (CTMU)”
26.0 “Special Features”
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Added Memory Maps for the new devices (see
Removed the BMXCHEDMA bit from the Bus Matrix Register map (see
Table
Added the REFOTRIM register, added the DIVSWEN bit to the REFOCON
registers, added Note 4 to the ULOCK and SOSCEN bits and added the
PBDIVRDY bit in the OSCCON register in the in the System Control Register
map (see
Removed the ALTI2C1 and ALTI2C2 bits from the DEVCFG3 register and
added Note 1 to the UPLLEN and UPLLIDIV<2:0> bits of the DEVCFG2
register in the Device Configuration Word Summary (see
Updated Note 1 in the Device and Revision ID Summary (see
Added Note 2 to the PORTA Register map (see
Added the ANSB6 and ANSB12 bits to the ANSELB register in the PORTB
Register map (see
Added Notes 2 and 3 to the PORTC Register map (see
Updated all register names in the Peripheral Pin Select Register map (see
Table
Added values in support of new devices (16 KB RAM and 32 KB RAM) in the
Data RAM Size register (see
Added values in support of new devices (64 KB Flash and 128 KB Flash) in
the Data RAM Size register (see
Added Note 5 to the PIC32MX1XX/2XX Family Clock Diagram (see
Figure
Added the PBDIVRDY bit and Note 2 to the Oscillator Control register (see
Register
Added the DIVSWEN bit and Note 3 to the Reference Oscillator Control
register (see
Added the REFOTRIM register (see
Updated the ADC1 Module Block Diagram (see
Updated the Notes in the ADC Input Select register (see
Updated the CTMU Block Diagram (see
Added Note 3 to the CTMU Control register (see
Added Note 1 and the PGEC4/PGED4 pin pair to the ICESEL<1:0> bits in
DEVCFG0: Device Configuration Word 0
Removed the ALTI2C1 and ALTI2C2 bits from the Device Configuration
Word 3 register (see
Removed 26.3.3 “Power-up Requirements”.
Added Note 3 to the Connections for the On-Chip Regulator diagram (see
Figure
Updated the Block Diagram of Programming, Debugging and Trace Ports
diagram (see
4-1).
4-23).
8-1).
26-2).
8-1).
Preliminary
Table
Register
Figure
4-16).
Table
26-3).
Register
8-3).
4-20).
Update Description
Register
26-4).
Register
Register
4-5).
Figure
(see
4-5).
8-4).
© 2011 Microchip Technology Inc.
Register
Figure 4-3
24-1).
Table
Figure
Register
4-19).
21-1).
26-1).
Table
Register
Table
24-1)
and
4-21).
Table
Figure
4-17).
21-4).
4-18).
4-4).

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