PIC32MX320F064HT-80I/PT Microchip Technology, PIC32MX320F064HT-80I/PT Datasheet - Page 12

64 KB Flash, 16 KB RAM, 40 MHz, 10-Bit ADC 64 TQFP 10x10x1mm T/R

PIC32MX320F064HT-80I/PT

Manufacturer Part Number
PIC32MX320F064HT-80I/PT
Description
64 KB Flash, 16 KB RAM, 40 MHz, 10-Bit ADC 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX320F064HT-80I/PT

Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
EUART, I2C, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC32MX320F064HT-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX
6.3
Format:
Purpose:
Description (in sequence):
FIGURE 6-5:
FIGURE 6-6:
DS61145G-page 12
oData = XferData (iData)
To clock data to and from the register selected by the
command.
1.
2.
3.
4.
The TMS Header is clocked into the device to
select the Shift DR state.
The data is clocked in/out of the device on
TDI/TDO while holding signal TMS low.
The last MSb of the data is clocked in/out
while setting TMS high.
The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
TMS
TCK
TDO
TDI
XferData Pseudo Operation
PGC
PGD
TDI = iLSb
TDI = 0
TDI = 0
‘1’
Data (31’h12) + TMS = 0
TMS Header = 100
XferData 4-WIRE
XferData 2-WIRE (4-PHASE)
TMS = 0
TMS = 1
TMS = 1
‘0’
TDO = oLSb+1
TDO =
TDO =
TMS Footer =
...
‘0’
X
X
TMS Header =
TDI = 0
oLSb
10
iLSb
TDI = 0
Data (32’h12)
TDI = iMSb
Data (MSb) + TMS Footer = 1
TMS = 0
TMS = 0
100
TMS = 1
Restrictions:
Example:
None.
oData = XferData (32’h12)
Data (MSb)
TDO =
+ TMS = 1
TDO =
oMSb
iMSb
‘1’
X
X
TDO =
TDI = 0
X
‘1’
TMS Footer = 10
© 2010 Microchip Technology Inc.
TMS = 0
‘0’
TDO = oLSb

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