PIC32MX564F064L-I/PT Microchip Technology, PIC32MX564F064L-I/PT Datasheet - Page 97
![100 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, CAN, 4 DMA 100 TQFP 12x12x1mm TRAY](/photos/18/28/182879/100-tqfp-pf_sml.jpg)
PIC32MX564F064L-I/PT
Manufacturer Part Number
PIC32MX564F064L-I/PT
Description
100 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, CAN, 4 DMA 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX564F064L-I/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Processor Series
PIC32MX5x
Core
MIPS32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX564F064L-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-34:
TABLE 4-35:
Legend:
Note
Legend:
Note
6180
6190 PORTG
61A0
61B0
61A0
61B0
6180
6190 PORTG
1:
1:
TRISG
ODCG
TRISG
ODCG
LATG
LATG
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
TRISG15
ODCG15
LATG15
31/15
31/15
RG15
—
—
—
—
—
—
—
—
—
—
—
—
TRISG14
ODCG14
LATG14
30/14
30/14
RG14
—
—
—
—
—
—
—
—
—
—
—
—
TRISG13
ODCG13
LATG13
29/13
29/13
RG13
—
—
—
—
—
—
—
—
—
—
—
—
TRISG12
ODCG12
LATG12
28/12
28/12
RG12
—
—
—
—
—
—
—
—
—
—
—
—
27/11
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG9
ODCG9
TRISG9
ODCG9
LATG9
LATG9
25/9
RG9
25/9
RG9
—
—
—
—
—
—
—
—
TRISG8
ODCG8
TRISG8
ODCG8
LATG8
LATG8
24/8
RG8
24/8
RG8
—
—
—
—
—
—
—
—
Bits
Bits
TRISG7
ODCG7
TRISG7
ODCG7
LATG7
LATG7
23/7
RG7
23/7
RG7
—
—
—
—
—
—
—
—
TRISG6
TRISG6
ODCG6
ODCG6
LATG6
LATG6
22/6
RG6
22/6
RG6
—
—
—
—
—
—
—
—
21/5
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
20/4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
Section 12.1.1 “CLR, SET and INV Registers”
TRISG3
ODCG3
TRISG3
ODCG3
LATG3
LATG3
19/3
19/3
RG3
RG3
—
—
—
—
—
—
—
—
(1)
(1)
TRISG2
ODCG2
TRISG2
ODCG2
LATG2
LATG2
18/2
RG2
18/2
RG2
—
—
—
—
—
—
—
—
TRISG1
ODCG1
LATG1
17/1
17/1
RG1
—
—
—
—
—
—
—
—
—
—
—
—
TRISG0
ODCG0
LATG0
16/0
16/0
RG0
—
—
—
—
—
—
—
—
—
—
—
—
for more
for more
0000
03CC
0000
xxxx
0000
xxxx
0000
0000
0000
F3CF
0000
xxxx
0000
xxxx
0000
0000
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