PIC32MX575F512HT-80I/MR Microchip Technology, PIC32MX575F512HT-80I/MR Datasheet - Page 109
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PIC32MX575F512HT-80I/MR
Manufacturer Part Number
PIC32MX575F512HT-80I/MR
Description
512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 64 QFN 9x9x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX575F512HT-80I/MR
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 4-46:
Legend:
Note
C100 C2FLTCON4
C120 C2FLTCON6
C130 C2FLTCON7
C140
C340
C350
C360
C370
C380
C110 C2FLTCON5
C2FIFOCONn
C2FIFOINTn
C2FIFOUAn
C2FIFOCIn
C2FIFOBA
1:
(n = 0-31)
(n = 0-31)
(n = 0-31)
(n = 0-31)
(n = 0-31)
C2RXFn
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16 FLTEN19
31:16 FLTEN23
31:16 FLTEN27
31:16 FLTEN31
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES
FLTEN17
FLTEN21
FLTEN25
FLTEN29
31/15
—
—
—
—
—
—
FRESET
30/14
MSEL19<1:0>
MSEL17<1:0>
MSEL23<1:0>
MSEL21<1:0>
MSEL27<1:0>
MSEL25<1:0>
MSEL31<1:0>
MSEL29<1:0>
—
—
—
—
—
29/13
UINC
—
—
—
—
—
DONLY
28/12
—
—
—
—
—
27/11
—
—
—
—
—
—
FSEL19<4:0>
FSEL17<4:0>
FSEL23<4:0>
FSEL21<4:0>
FSEL27<4:0>
FSEL25<4:0>
FSEL31<4:0>
FSEL29<4:0>
TXNFULLIE TXHALFIE TXEMPTYIE
TXNFULLIF TXHALFIF TXEMPTYIF
SID<10:0>
26/10
—
—
—
—
25/9
—
—
—
—
(1)
(CONTINUED)
C2FIFOBA<31:0>
C2FIFOUA<31:0>
24/8
—
—
—
—
EID<15:0>
Bits
FLTEN18
FLTEN16
FLTEN22
FLTEN20
FLTEN26
FLTEN24
FLTEN30
FLTEN28
TXEN
23/7
—
—
—
—
—
TXABAT
22/6
MSEL18<1:0>
MSEL16<1:0>
MSEL22<1:0>
MSEL20<1:0>
MSEL26<1:0>
MSEL24<1:0>
MSEL30<1:0>
MSEL28<1:0>
—
—
—
—
—
TXLARB
21/5
—
—
—
—
—
TXERR
Section 12.1.1 “CLR, SET and INV Registers”
20/4
-—
—
—
—
RXOVFLIE RXFULLIE RXHALFIE
RXOVFLIF RXFULLIF RXHALFIF
TXREQ
EXID
19/3
—
C2FIFOCI<4:0>
FSEL18<4:0>
FSEL22<4:0>
FSEL20<4:0>
FSEL26<4:0>
FSEL24<4:0>
FSEL30<4:0>
FSEL28<4:0>
FSEL16<4:0:
FSIZE<4:0>
RTREN
18/2
—
—
17/1
—
EID<17:16>
TXPRI<1:0>
EMPTYIE
EMPTYIF
for more
16/0
RXN
RXN
—
0000
0000
0000
0000
0000
0000
0000
0000
xxxx
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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