PIC32MX575F512HT-80I/PT Microchip Technology, PIC32MX575F512HT-80I/PT Datasheet - Page 89
PIC32MX575F512HT-80I/PT
Manufacturer Part Number
PIC32MX575F512HT-80I/PT
Description
512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
Specifications of PIC32MX575F512HT-80I/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX575F512HT-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC32MX320F032H-40IPT PDF datasheet
- PIC32MX575F256H-80IMR PDF datasheet #2
- PIC32MX575F256H-80IMR PDF datasheet #3
- PIC32MX575F256H-80IMR PDF datasheet #4
- Current page: 89 of 254
- Download datasheet (6Mb)
TABLE 4-19:
Legend:
Note
35F0 DCH7SSIZ
3600 DCH7DSIZ
3610 DCH7SPTR
3620 DCH7DPTR
3630 DCH7CSIZ
3640 DCH7CPTR
3650
1:
DCH7DAT
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
DMA CHANNELS 0-7 REGISTER MAP
31/15
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
(1,2)
26/10
(CONTINUED)
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
24/8
CHSPTR<15:0>
CHDPTR<15:0>
CHCPTR<15:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHCSIZ<15:0>
—
—
—
—
—
—
—
—
Bits
23/7
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
20/4
Section 12.1.1 “CLR, SET and INV Registers”
CHPDAT<7:0>
—
—
—
—
—
—
—
19/3
—
—
—
—
—
—
—
18/2
—
—
—
—
—
—
—
17/1
—
—
—
—
—
—
—
for more
16/0
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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