S29AS008J70BFI030 Spansion Inc., S29AS008J70BFI030 Datasheet - Page 16

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S29AS008J70BFI030

Manufacturer Part Number
S29AS008J70BFI030
Description
IC 8M FLASH MEMORY
Manufacturer
Spansion Inc.
Datasheet

Specifications of S29AS008J70BFI030

Cell Type
NOR
Density
8Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Bottom/Top
Address Bus
20/19Bit
Operating Supply Voltage (typ)
1.8V
Operating Temp Range
-40C to 85C
Package Type
FBGA
Program/erase Volt (typ)
1.65 to 1.95V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.65V
Operating Supply Voltage (max)
1.95V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
12mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant
7.7
7.8
7.9
16
RESET#: Hardware Reset Pin
Output Disable Mode
Autoselect Mode
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin to V
progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (I
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of t
RESET# pin returns to V
Refer to the tables in
for the timing diagram. If V
Temporary Sector Group Unprotect mode. See
details on this feature.
When the OE# input is at V
impedance state.
The autoselect mode provides manufacturer and device identification, sector group protection verification,
and Secured Silicon Sector status through identifier codes output on DQ7–DQ0. This mode is primarily
intended for programming equipment to automatically match a device to be programmed with its
corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires V
Address pins A6, A3, A2, A1, and A0 must be as shown in
protection, the sector address must appear on the appropriate highest order address bits (see
on page 17
all necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in
Definitions on page 28
and
Table 7.4 on page
AC Characteristics on page 43
for details on using the autoselect mode.
IH
.
ID
IL
READY
IH
(9.0 V – 11.0 V) is applied to the RESET# pin, the device will enter the
, output from the device is disabled. The output pins are placed in the high
for at least a period of t
CC4
Table 11.1 on page
(not during Embedded Algorithms). The system can read data t
18).
). If RESET# is held at V
Table 7.2
S29AS008J
D a t a
Temporary Sector Group Unprotect on page 21
shows the remaining address bits that are don’t care. When
RP
33. This method does not require V
for RESET# parameters and to
, the device immediately terminates any operation in
S h e e t
Table
IL
READY
but not within V
7.2. In addition, when verifying sector group
(during Embedded Algorithms). The
ID
(9.0 V to 11.0 V) on address pin A9.
S29AS008J_00_08 July 16, 2009
SS
±0.2 V, the standby current
Figure 18.2 on page 44
SS
±0.2 V, the device
ID
. See
Table 7.3
Command
for more
RH
after the

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