SC657ULTRT Semtech, SC657ULTRT Datasheet - Page 14

• Manufacturer Part Number: SC657ULTRT
• Description: Backlight Driver For 5 LEDs With SemPulseTM Interface
• Manufacturer: Semtech

SemPulse
Introduction
SemPulse is a write-only single wire interface. It provides
the capability to access up to 32 registers that control
device functionality. Two sets of pulse trains are transmit-
ted via the SPIF pin. The first pulse set is used to set the
desired address. After the bus is held high for the address
hold period, the next pulse set is used to write the data
value. After the data pulses are transmitted, the bus is
held high again for the data hold period to signify the data
write is complete. At this point the device latches the data
into the address that was selected by the first set of pulses.
See the SemPulse Timing Diagrams for descriptions of all
timing parameters.
Chip Enable/Disable
The device is enabled when the SemPulse interface pin
(SPIF) is pulled high for greater than t
pulled low again for more than t
disabled.
Address Writes
The first set of pulses can range between 0 and 3 (or  to
32 rising edges) to set the desired address. After the
pulses are transmitted, the SPIF pin must be held high for
t
finished. If the pulse count is between 0 and 3 and the
line is held high for t
destination for the next data write. If the SPIF pin is not
held high for t
pulses. Note that if t
tion, the bus will reset. This means that the communication
is ignored and the bus resumes monitoring the pin,
expecting the next pulse set to be an address. If the total
exceeds 3 pulses, SPIF must be held high until the bus
reset time t
communication.
Data Writes
After the bus has been held high for the minimum address
hold period, the next set of pulses are used to write the
data value. The total number of pulses can range from 0
to 63 (or  to 64 rising edges) since there are a total of 6
HOLDA
to signal to the slave device that the address write is
TM
HOLDA
BR
Interface
is exceeded before commencing
, the slave device will continue to count
HOLDA
HOLDA
exceeds its maximum specifica-
, the address is latched as the
SD
, the device will be
SU
. If the SPIF pin is
register bits per register. Just like with the address write,
the data write is only accepted if the bus is held high for
t
hold time is not received, the interface will keep counting
pulses until the hold time is detected. If the total exceeds
63 pulses, the write will be ignored and the bus will reset
after the next valid hold time is detected. After the bus
has been held high for t
pulse set to be an address write. Note that this is the same
effect as the bus reset that occurs when t
maximum specification. For this reason, there is no
maximum limit on t
next valid address to be transmitted.
Multiple Writes
It is important to note that this single-wire interface
requires the address to be paired with its corresponding
data. If it is desired to write multiple times to the same
address, the address must always be re-transmitted prior
to the corresponding data. If it is only transmitted one
time and followed by multiple data transmissions, every
other block of data will be treated like a new address. The
result will be invalid data writes to incorrect addresses.
Note that multiple writes only need to be separated by
the minimum t
rectly. As long as t
the data pulse set is less than its maximum specification
but greater than its minimum, multiple pairs of address
and data pulse counts can be made with no detrimental
effects.
Standby Mode
Once data transfer is completed, the SPIF line must be
returned to the high state for at least 0ms to return to the
standby mode. In this mode, the SPIF line remains idle
while monitoring for the next command. This mode
allows the device to minimize current consumption
between commands. Once the device has returned to
standby mode, the bus is automatically reset to expect the
address pulses as the next data block. This safeguard is
intended to reset the bus to a known state (waiting for the
beginning of a write sequence) if the delay exceeds the
reset threshold.
HOLDD
when the pulse train is completed. If the proper
HOLDD
HOLDA
HOLDD
for the slave to interpret them cor-
between the address pulse set and
HOLDD
— the bus simply waits for the
, the bus will expect the next
HOLDA
exceeds its
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