SERDESUB-16USB/NOPB National Semiconductor, SERDESUB-16USB/NOPB Datasheet - Page 20

• Manufacturer Part Number: SERDESUB-16USB/NOPB
• Description: EVAL BOARD FOR DS90UB901/2
• Manufacturer: National Semiconductor
• Series: -r

Specifications of SERDESUB-16USB/NOPB

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Embedded: No
• Utilized Ic / Part: DS90UB901Q
• Primary Attributes: Bidirectional Control with I2C Support
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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(Hex)
Addr
TABLE 1. DS90UB901Q Control Registers
0
1
2
3
4
VDDIO Control
I
Transmission
VDDIO Mode
PCLK_AUTO
Transmission
2
RESERVED
C Device ID
CRC Fault
Reserved
I
Tolerant
2
Through
C Pass-
Name
Reset
TRFB
CRC
Bits
7:1
7:3
7:0
7:6
4:0
0
2
1
0
7
6
5
4
3
2
1
0
5
Field
DEVICE ID
SER ID SEL
RESERVED
STANDBY
DIGITAL
RESET0
DIGITAL RESET1
RESERVED
RX CRC
CHECKER
ENABLE
TX CRC GEN
ENABLE
VDDIO CONTOL
VDDIO MODE
I
THROUGH
RESERVED
PCLK_AUTO
TRFB
RESERVED
CRC RESET
RESERVED
2
C PASS-
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
20
self clear
self clear
00000'b
Default
0xB0'h
0x00'h
0x20'h
10'b
0
0
0
1
1
1
1
1
0
1
1
0
Description
7-bit address of Serializer; 0x58'h
(1011_000X'b) default
0: Device ID is from ID[x]
1: Register I
Reserved
Standby mode control. Retains control register data.
Supported only when MODE = 0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
1: Resets the device to default register values. Does not
affect device I
1: Digital Reset, retains all register values
Reserved
Back Channel CRC Enable
0: Disable
1: Enable
For proper CRC operation, on Deserailizer 0x03h b[6]
control register must be Enabled.
Foward Channel CRC Enable
0: Disable
1: Enable
For proper CRC operation, on Deserailizer 0x03h b[7]
control register must be Enabled.
Auto V
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I
0: Disabled
1: Enabled
Reserved
Switch over to internal 25 MHz Oscillator clock in the
absence of PCLK
0: Disable
1: Enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
Reserved
1: CRC Reset.
Clears CRC Error counter.
Reserved
2
C Pass-Through
DDIO
detect
2
C Device ID overrides ID[x]
2
C Bus or Device ID