SST25VF010A-33-4C-SAE-T Microchip Technology, SST25VF010A-33-4C-SAE-T Datasheet - Page 7

• Manufacturer Part Number: SST25VF010A-33-4C-SAE-T
• Description: 2.7V To 3.6V 1Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF010A-33-4C-SAE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 33MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 Mbit SPI Serial Flash
SST25VF010A
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table 5, to be software pro-
tected against any memory Write (Program or Erase)
operations. The Write-Status-Register (WRSR) instruction
is used to program the BP1 and BP0 bits as long as WP#
is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase
can only be executed if Block-Protection bits are both 0.
After power-up, BP1 and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (V
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP# pin is driven high (V
its value is “Don’t Care”. After power-up, the BPL bit is
reset to 0.
©2006 Silicon Storage Technology, Inc.
IL
), enables the Block-Protection-
IH
), the BPL bit has no effect and
7
TABLE 5: S
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit pro-
vides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
3 (Full Memory Array)
1 (1/4 Memory Array)
2 (1/2 Memory Array)
Protection Level
1. Default at power-up for BP1 and BP0 is ‘11’.
0
B
OFTWARE
LOCK
P
ROTECTION
Register Bit
BP1
S
0
0
1
1
Status
TATUS
BP0
0
1
0
1
R
1
EGISTER
018000H-01FFFFH
010000H-01FFFFH
000000H-01FFFFH
S71265-02-000
Memory Area
Protected
None
Data Sheet
T5.0 1265
1/06