SST49LF008A-33-4C-EIE-T Microchip Technology, SST49LF008A-33-4C-EIE-T Datasheet - Page 13

• Manufacturer Part Number: SST49LF008A-33-4C-EIE-T
• Description: 3.0V To 3.6V 8Mbit LPC Firmware Flash 40 TSOP 10x20 Mm T/R
• Manufacturer: Microchip Technology

Specifications of SST49LF008A-33-4C-EIE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 40-TFSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 Mbit Firmware Hub
SST49LF008A
TABLE 4: FWH Write Cycle
©2006 Silicon Storage Technology, Inc.
FIGURE 7: Write Waveforms
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
3-9
10
11
12
13
14
15
16
17
1
2
FWH[3:0]
FWH4
CLK
IMADDR
RSYNC
IMSIZE
START
IDSEL
Name
Field
DATA
DATA
TAR0
TAR1
TAR0
TAR1
STR
IDS
Field Contents
0000 to 1111
0000 (1 byte)
1111 (float)
1111 (float)
FWH[3:0]
YYYY
YYYY
YYYY
1110
1111
0000
1111
1
IMADDR
OUT then Float
Float then OUT The SST49LF008A takes control of the bus during this
IN then Float
Float then IN
FWH[3:0]
Direction
OUT
IN
IN
IN
IN
IN
IN
13
Comments
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitions high)
should be recognized. The START field contents indi-
cate a FWH memory Read cycle.
Indicates which SST49LF008A device should
respond. If the IDSEL (ID select) field matches the
value ID[3:0], then that particular device will respond
to the whole bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
This size field indicates how many bytes will be
transferred during multi-byte operations. The FWH
only supports single-byte writes. IMSIZE=0000b
This field is the least-significant nibble of the data byte.
This data is either the data to be programmed into the
flash memory or any valid flash command.
This field is the most-significant nibble of the data byte.
In this clock cycle, the master (Intel ICH) has driven the
then float bus to all ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus
“turnaround cycle.”
cycle. During the next clock cycle it will be driving the
“sync” data.
The SST49LF008A outputs the values 0000, indicating
that it has received data or a flash command.
In this clock cycle, the SST49LF008A has driven the
bus to all then float ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus
“turnaround cycle.”
The master (Intel ICH) resumes control of the bus during
this cycle.
IMS
DATA
TAR
RSYNC
TAR
1161 F10.0
S71161-11-000
Data Sheet
T4.4 1161
3/06