SST49LF016C-33-4C-WHE-T Microchip Technology, SST49LF016C-33-4C-WHE-T Datasheet
SST49LF016C-33-4C-WHE-T
Specifications of SST49LF016C-33-4C-WHE-T
Related parts for SST49LF016C-33-4C-WHE-T
SST49LF016C-33-4C-WHE-T Summary of contents
Page 1
... Status register for End-of-Write detection – Program-/Erase-Suspend Read or Write to other blocks during Program-/Erase-Suspend PRODUCT DESCRIPTION The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that support a low- pin-count (LPC) interface for system firmware applications. Complying with ...
Page 2
... Program operation and 2.5 µs per byte with a quad-byte Program operation. The SST49LF016C is offered in 32-PLCC, 32-TSOP , and 40-TSOP packages. See Figures 3, 4, and 5 for pin assign- ments and Table 1 for pin descriptions. ©2008 Silicon Storage Technology, Inc. ...
Page 3
... Mbit LPC Serial Flash SST49LF016C FUNCTIONAL BLOCKS TBL# WP# INIT# LAD[3:0] LCLK LPC LFRAME# Interface ID[3:0] GPI[4:0] AAI AAI Interface RY/BY# LD# FIGURE 1: Functional Block Diagram ©2008 Silicon Storage Technology, Inc. X-Decoder Address Buffers & Latches Control Logic RST# 3 Data Sheet SuperFlash Memory ...
Page 4
... Block 22 160000H 15FFFFH Block 21 150000H 14FFFFH Block 20 140000H 13FFFFH Block 19 130000H 12FFFFH Block 18 120000H FIGURE 2: Device Memory Map for SST49LF016C ©2008 Silicon Storage Technology, Inc. Boot Block WP# for Block 0~33 (64 KByte Mbit LPC Serial Flash SST49LF016C 11FFFFH Block 17 110000H 10FFFFH Block 16 ...
Page 5
... Mbit LPC Serial Flash SST49LF016C PIN ASSIGNMENTS ( ) Designates AAI Mode FIGURE 3: Pin Assignments for 32-lead PLCC GPI4 LCLK NC NC RST# GPI3 GPI2 GPI1 (LD#) GPI0 (RY/BY#) WP#/AAI TBL Designates AAI Mode FIGURE 4: Pin Assignments for 32-lead TSOP ©2008 Silicon Storage Technology, Inc. ...
Page 6
... NC NC RST GPI3 GPI2 GPI1 (LD#) GPI0 (RY/BY#) WP#/AAI TBL Designates AAI Mode FIGURE 5: Pin Assignments for 40-lead TSOP ©2008 Silicon Storage Technology, Inc 40-lead TSOP 10 11 Top View Mbit LPC Serial Flash SST49LF016C LFRAME# 37 INIT LAD3 27 LAD2 26 LAD1 25 LAD0 24 ID0 23 ID1 22 ...
Page 7
... Mbit LPC Serial Flash SST49LF016C PIN DESCRIPTIONS TABLE 1: Pin Description 1 Symbol Pin Name Type LCLK Clock I LAD[3:0] Address I/O and Data LFRAME# Frame I RST# Reset I INIT# Initialize I ID[3:0] Identification I Inputs GPI[4:0] General I Purpose Inputs TBL# Top Block Lock I WP#/AAI Write Protect ...
Page 8
... Write Protect / Top Block Lock The Top Boot Lock (TBL#) and Write Protect (WP#/AAI) pins are provided for hardware write protection of device memory in the SST49LF016C. The TBL# pin is used to write protect 16 KByte at the highest memory address range for the SST49LF016C. WP#/AAI pin write protects the remaining sectors in the flash memory ...
Page 9
... The Load Enable pin (LD#), is an input pin which when low, indicates the host is loading data in an AAI programming cycle. Data is loaded in the SST49LF016C at the rising edge of the clock. If LD# is high, it signals the AAI interface that the host is terminating the command. LD# low/high switches the RY/BY# output from buffer free flag to pro- gramming complete flag (see Table 18) ...
Page 10
... IN The MSIZE field indicates how many bytes will be trans- ferred during multi-byte operations. Device will execute multi-byte read of 2 SST49LF016C supports only MSIZE = ( 16, 128 Bytes), with KKKK=0000b, 0001b, 0010b, 0100b, or 0111b. IN, In this clock cycle, the master has driven the bus to all ‘1’s then Float and then floats the bus, prior to the next clock cycle ...
Page 11
... In this clock cycle, the master has driven the bus to all ‘1’s and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” A=(10+2 Float then OUT The SST49LF016C takes control of the bus during this cycle. A=(10+2 0000 ...
Page 12
... Response to Invalid Fields for Firmware Memory Cycle During an on-going Firmware Memory bus cycle, the SST49LF016C will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is described as follows: ID mismatch: If the IDSEL field does not match ID[3:0], the device will ignore the cycle. See “ ...
Page 13
... For Firmware Memory Read/Write cycles, hardware strap- ping values on ID[3:0] must match the values in IDSEL field. The SST49LF016C will compare these bits with ID[3:0]’s strapping values. If there is a mismatch, the device will ignore the remainder of the cycle. See Table 7 for Multi- ple Device Selection Configuration. © ...
Page 14
... User-Security-ID-Program-Lockout 1. This value must be a valid address within the device Memory Address Space. X can SST Manufacturer’ BFH, is read with A SST49LF016C Device ID = 5CH, is read with A Following the Read-Software-ID/Read-Security-ID command, Read operations access Manufacturer’s ID and Device ID or Security ID. 3. Following the Read-Software-ID/Read-Security-ID command, Read operations access manufacturer’s ID and Device ID or Security ID ...
Page 15
... Silicon Storage Technology, Inc. TABLE 9: Product Identification Manufacturer’s ID FFFC 0000H Device ID SST49LF016C FFFC 0001H 1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system ...
Page 16
... Erase cannot resume until any Program operation ini- tiated during Erase-Suspend has completed. Suspended operations cannot be nested: the system needs to com- plete or resume any previously suspended operation before a new operation can be suspended. See Figure 8 for flowchart. 16 SST49LF016C (10 µs). The device ES S71237-08-000 5/08 ...
Page 17
... µs). BP Security ID Commands The SST49LF016C device offers a 256-bit Security ID space. The Security ID space is divided into two parts. One 64-bit segment is programmed at SST with a unique 64-bit number: this number cannot be changed by the user. The other segment is 192-bit wide and is left blank: this space is available for customers and can be programmed as desired ...
Page 18
... General Purpose Inputs Register The General Purpose Inputs register (GPI_REG) passes the state of GPI[4:0] pins on the SST49LF016C rec- ommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. ...
Page 19
... Mbit LPC Serial Flash SST49LF016C Block Locking Registers SST49LF016C provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and they are accessible through standard addressable memory locations specified in Table 14. Unused register locations will return 00H if read ...
Page 20
... The read lock status can be unlocked by clearing the read lock bit: this can only be done provided that the block is not locked down. The current read lock status of a particular block can be deter- mined by reading the corresponding read-lock bit. 20 SST49LF016C T15.0 1237 S71237-08-000 5/08 ...
Page 21
... Mbit LPC Serial Flash SST49LF016C Security ID Registers The SST49LF016C device offers a 256-bit Security ID reg- ister space. The Security ID space is divided into two seg- ments - one (64-bits) factory programmed segment and one (192 bits) user programmed segment. The first seg- ment is programmed and locked at SST with a unique 64- bit number ...
Page 22
... RY/BY# returns to high indicating the completion of the AAI cycle. Software block-locking will be disabled in AAI mode (all blocks will be write-unlocked). If AAI drops below the Supervoltage V H LD# high), the contents of the page may be indeterminate Mbit LPC Serial Flash SST49LF016C ) to end the data indicate the AAI command byte byte ...
Page 23
... The START field contents indicate a Firmware Memory Write cycle. (1110b works identically to Firmware Memory cycle. This field indicates which SST49LF016C device should respond. If the IDSEL (ID select) field matches the value of ID[3:0], then that particular device will respond to the whole bus cycle. ...
Page 24
... C capable in both non-Pb and with-Pb solder versions. ° C for 10 seconds; please consult the factory for the latest information 3.0-3. Mbit LPC Serial Flash SST49LF016C +0. -2.0V to +2. S71237-08-000 5/08 ...
Page 25
... Mbit LPC Serial Flash SST49LF016C DC Characteristics TABLE 20: DC Operating Characteristics at 33 MHz and 66 MHz (All Interfaces) Symbol Parameter 1 I Active V Current DD DD Read Single-/Dual-Byte Program, Erase Quad-Byte Program I Standby V Current SB DD (LPC Interface Ready Mode V Current Input Leakage Current for ID[3:0] pins ...
Page 26
... MHz Min Max CYC T HIGH T LOW 0 0 Mbit LPC Serial Flash SST49LF016C Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 T23.0 1237 66 MHz Units Min Max 15 ns 6 V/ns 50 mV/ns T24.0 1237 ...
Page 27
... Mbit LPC Serial Flash SST49LF016C TABLE 25: Reset Timing Parameters, V Symbol Parameter T V stable to Reset High PRST DD T RST# Pulse Width RSTP T RST# Low to Output Float RSTF 1 T RST# High to LFRAME# Low RST T RST# Low to reset during Sector-/Block-Erase or Program RSTE 1. There will be a latency due to T ...
Page 28
... Mode MHz Min Min Max - -17.1 OUT 1 Equation C - Equation D DD 26.7 V OUT -25+(V +1)/0.015 IN 25+(V -V -1)/0.015 Mbit LPC Serial Flash SST49LF016C 66 MHz Max Min Max Units µ µ T26.0 1237 Units Conditions ≤ 0. < V OUT DD mA 0.3V < V < 0.9V ...
Page 29
... Mbit LPC Serial Flash SST49LF016C (Valid Output Data) (Float Output Data) FIGURE 12: Output Timing parameters (LPC Mode) LCLK LAD [3:0] (Valid Input Data) FIGURE 13: Input Timing Parameters (LPC Mode) TABLE 28: Interface Measurement Condition Parameters (LPC Mode) Symbol TEST 1 V MAX Input Signal Edge Rate 1 ...
Page 30
... T LD# Set Up Time LDSU T LD# Hold Time LDDH ©2008 Silicon Storage Technology, Inc. 16 Mbit LPC Serial Flash T ACYC V TEST T ASU T ADH Inputs Valid T LDSU T LDDH T RB =3.0-3.6V (AAI Mode) DD Min 135 SST49LF016C MAX 1237 F13.3 Max Units T29.3 1237 S71237-08-000 5/08 ...
Page 31
... Mbit LPC Serial Flash SST49LF016C V IHT INPUT V ILT AC test inputs are driven at V (0.9 IHT points for inputs and outputs are V FIGURE 15: AC Input/Output Reference Waveforms TO DUT FIGURE 16: A Test Load Example ©2008 Silicon Storage Technology, Inc. V REFERENCE POINTS IT ) for a logic “1” and V (0 ...
Page 32
... XX - SST49LF xxxC - XX - Valid combinations for SST49LF016C SST49LF016C-33-4C-NHE SST49LF016C-33-4C-WHE SST49LF016C-33-4C-EIE SST49LF016C-66-4C-NHE SST49LF016C-66-4C-WHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2008 Silicon Storage Technology, Inc. ...
Page 33
... Mbit LPC Serial Flash SST49LF016C PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional .447 Pin #1 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). ...
Page 34
... Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. FIGURE 18: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2008 Silicon Storage Technology, Inc. 8.10 7.90 1.20 max. 14.20 13. Mbit LPC Serial Flash SST49LF016C 1.05 0.95 0.50 BSC 0.27 0.17 0.15 0.05 DETAIL 0°- 5° 0.70 ...
Page 35
... Mbit LPC Serial Flash SST49LF016C Pin # 1 Identifier 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. ...
Page 36
... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2008 Silicon Storage Technology, Inc. Description www.SuperFlash.com or www.sst.com 36 16 Mbit LPC Serial Flash SST49LF016C Date Oct 2003 Nov 2003 Apr 2004 Dec 2004 Jul 2005 ...