SX8652ICSTRT Semtech, SX8652ICSTRT Datasheet - Page 15

• Manufacturer Part Number: SX8652ICSTRT
• Description: 4/5-wire Resistive Touch Screen Controller (SPI)
• Manufacturer: Semtech

6. Data Processing
The SX8652 offers 4 types of data processing which allows the user to make trade-offs between data throughput, power
consumption and noise rejection. The parameter FILT is used to select the filter order N
The sn samples from the ADC can be averaged. The processed cn 12-bit value is then send through the SPI bus.
The noise rejection will be improved with a high order to the detriment of the power consumption.
The K coefficient in Table 8 is a filter constant. Its value is K=4079/4095.
7. Power-Up, Reset
During power-up, NIRQ pin is kept low, the POR reset all
registers and states of the SX8652. The SX8652 is not
accessible and SPI communications are ignored.
As soon as NIRQ rises, the SX8652 is in manual mode with
only
consumption.
The host can reset the SX8652 by setting the NRST pin low or
via the SPI bus. Writing the code 0xDE to the register
RegSoftReset reset the circuit.
When NRST is driven LOW by the host, NIRQ will be driven low
by the SX8652. After the reset NIRQ will be released by the
SX8652.
8. Modes of Operation
The SX8652 has four operation modes that are configured using the SPI commands as defined in Table 13 and Table 15.
These 4 modes are:
Revision V1.7/October 2010
©2010 Semtech Corp.
ADVANCED COMMUNICATIONS & SENSING
manual (command ‘MANAUTO’ and RATE=0),
automatic (command ‘MANAUTO’ and RATE>0),
pen detect (command ‘PENDET’),
pen trigger mode (command ‘PENTRG’).
FILT
0
1
2
3
the
SPI
N
1
3
5
7
filt
peripheral
7 ADC samples are sorted and
3 ADC samples are averaged
5 ADC samples are averaged
the 3 center samples are
Explanation
No average
averaged
enabled
to
minimize
Table 8. Filter order
s n
c max1
s n
s n
s n
=
=
=
15kV ESD Low Power 4-Wire / 5-Wire Resistive
=
c n
power
1
-- -
3
Page 15
1
-- -
5
1
-- -
3
K
K
K
c max2
c n
c n
c a
+
+
Touchscreen Controller with SPI Interface
+
c n 1
c n 1
c b
–
–
c a
+
voltage
voltage
NIRQ
c c
VDD/2
VDD
+
+
c b
c n 2
c n 2
–
–
c c
Processing
+
c n 3
c min1
–
filt
+
as seen in Table 8.
c n 4
c min2
Figure 13. Power-up, NIRQ
t
POR
–
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