SY87701ALHG Micrel Inc, SY87701ALHG Datasheet - Page 4

• Manufacturer Part Number: SY87701ALHG
• Description: 3.3V Any Rate 32-1250 Mbps CDR (I Temp, Green/32 Pin EP-TQFP/Bulk)
• Manufacturer: Micrel Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SY87701ALHG

• Input: PECL, TTL
• Output: PECL, TTL
• Frequency - Max: 1.3GHz
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP Exposed Pad, 32-eTQFP, 32-HTQFP, 32-VQFP
• Frequency-max: 1.3GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1585

M9999-082107
[e-mail] or [phone]
Micrel, Inc.
Clock Recovery
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The clock is
phase aligned by a PLL so that it samples the data in the
center of the data eye pattern.
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, then PLL will be
declared out of lock, and the PLL will lock to the reference
clock.
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30 s data stream of continuous
1's or 0's for random incoming NRZ data.
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
FUNCTIONAL DESCRIPTION
Clock Recovery, as shown in the block diagram,
The phase relationship between the edge transitions of
Frequency stability without incoming data is guaranteed
The loop filter transfer function is optimized to enable the
The total loop dynamics of the clock recovery PLL
4
Lock Detect
that monitors the integrity of the serial data input. If the
recovered serial data from RDIN is at the correct data rate
(within 1000ppm of the synthesizer frequency), the Link
Fault Indicator (LFIN) output will be asserted HIGH indicating
an in-lock condition and will remain HIGH as long as this
condition is met.
correct data rate (greater than 1000ppm difference from the
synthesizer frequency), then LFIN output will go LOW
indicating an out-of-lock condition. This condition will force
the Clock and Data Recovery PLL (CDR) to lock onto the
synthesizer frequency until it is within the correct frequency
range (less than 1000ppm difference from the synthesizer
frequency). Once the CDR is within the correct frequency
range it will again lock onto the RDIN input.
RDIN input, the LFIN output will not be a static LOW, but
will be changing.
The SY87701AL contains a link fault indication circuit
In the event that the recovered serial data is not at the
During the interval when the CDR is not locked onto the
SY87701AL