SY89327LMG TR Micrel Inc, SY89327LMG TR Datasheet - Page 2
SY89327LMG TR
Manufacturer Part Number
SY89327LMG TR
Description
3.3V Ultrasmall Any-Input-to-LVPECL Translator (I Temp, Green)
Manufacturer
Micrel Inc
Series
SY89r
Datasheet
1.SY89327LMG_TR.pdf
(8 pages)
Specifications of SY89327LMG TR
Logic Function
Translator
Number Of Bits
1
Input Type
CML, CMOS, HSTL, LVDS, TTL
Output Type
LVPECL
Data Rate
2.5Gbps
Number Of Channels
1
Number Of Outputs/channel
1
Differential - Input:output
Yes/Yes
Propagation Delay (max)
0.4ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-MLF®, QFN
Supply Voltage
3 V ~ 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-1419-2
Micrel, Inc.
Establishing Static Logic Inputs
complement input to ground. A logic zero is achieved by
connecting the complement input to ground with the true
input floating. For a TTL input, tie a 2.5kΩ resistor between
the complement input and ground. See “Input Interface”
section.
Input Levels
connected directly to the D inputs. Depending on the actual
worst case voltage seen, the SY8327L's performance varies
as per the following table:
M9999-071707
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
FUNCTIONAL DESCRIPTION
Do not leave unused inputs floating. Tie either the true or
LVDS, CML, and HSTL differential signals may be
0 to V
Input Voltage
PIN DESCRIPTION
Pin Number
0 to 2.4V
NC
NC
Range
/IN
IN
CC
2, 3
7, 6
1, 4
8
5
1
2
3
4
+0.3V
8-Pin MLF
Exposed Pad
Voltage Swing
Pin Name
®
Minimum
IN, /IN
GND,
100mV
200mV
Q, /Q
8
7
6
5
VCC
NC
VCC
Q
/Q
GND
Pin Function
Differential inputs: This input is the differential signal input to the device. This input
accepts AC- or DC-coupled signals as small as 100mV. External termination is required.
Please refer to the “Input Interface Applications” section for more details.
Positive power supply. Bypass with 0.1µF0.01µF low ESR capacitors.
Differential LVPECL Output: Terminate with 50Ω to V
Applications” section. Output pair is 100k temperature compensated LVPECL compatible.
Ground: Ground pin and exposed pad must be connected to the same ground plane.
No connect.
Translation Speed
Ordering Information
Part Number
SY89327LMITR
SY89327LMGTR
Maximum
1.25Gbps
2.5Gbps
2
supported. Due to the current required by the input structure
shown in Figure 1, multi-drop and multi-point architectures
are not supported.
Package
MLF-8
MLF-8
Type
For LVDS applications, only point-to-point interfaces are
Figure 1. Simplified Input Structure
Operating
/D
Industrial
Industrial
D
Range
IN
IN
1.05kΩ
1.05kΩ
R1
R1
1.5kΩ
CC
Pb-Free bar-line indicator
R2
–2V. See “Output Interface
Package
Marking
327 with
GND
V
327
CC
R2
1.5kΩ
Precision Edge®
SY89327L
Pb-Free
NiPdAu
Finish
Sn-Pb
Lead