S2004TB Applied Micro Circuits Corporation, S2004TB Datasheet - Page 10

• Manufacturer Part Number: S2004TB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2004TB

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

RECEIVER DESCRIPTION
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 5.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2004 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the decoded data on its parallel outputs.
The S2004 provides the capability to operate with all
four channels locked together (CHANNEL LOCK
mode). Channel lock process and status reporting is
described below.
Data Input
A differential input receiver is provided for each
channel of the S2004. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for each channel is enabled by its respective LPEN
input.
The high speed serial inputs to the S2004 are inter-
nally biased to VDD-1.3V. All that is required exter-
nally is AC-coupling and line-to-line differential
termination.
Clock Recovery Function
Clock recovery is performed on the input data
stream for each channel of the S2004. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
Table 6. Lock to Reference Frequency Criteria
10
S2004
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the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the VCO to lock to the refer-
ence clock. This allows the VCO to maintain the cor-
rect frequency in the absence of data.
The ‘lock to reference’ frequency criteria insure that
the S2004 will respond to variations in the serial data
input frequency (compared to the reference fre-
quency). The new Lock State is dependent upon the
current lock state, as shown in Table 6.
The run-length criteria insure that the S2004 will re-
spond appropriately and quickly to a loss of signal.
The run-length checker flags a condition of consecu-
tive ones or zeros across 12 parallel words. Thus
119 or less consecutive ones or zeros does not
cause signal loss, 129 or more causes signal loss,
and 120 - 128 may or may not, depending on how
the data aligns across byte boundaries.
If both the off-frequency detect circuitry test and the
run-length test are satisfied, the CRU will attempt to
lock to the incoming data. When lock is achieved,
LOCK-DET is asserted on the ERR, EOF, and
KFLAG status lines. It is possible for the run length
test to be satisfied due to noise on the inputs, even if
no signal is present. In this case the lock detect sta-
tus may periodically assert as the VCO frequency
approaches that of the REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RCxP/N outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
When operating in independent mode, PLL lock sta-
tus for each channel is indicated by a 1-0-1 on its
respective ERR, EOF, and KFLAG outputs, respec-
tively. When operating in the CHANNEL LOCK
mode, PLL locking of all four channels must be ac-
complished before byte-skewing is achieved and “in
sync” status is indicated on the ERR, EOF, and
KFLAG outputs.
Reference Clock Input
A single reference clock, which serves both transmit-
ter and receiver, must be provided from a low jitter
clock source. The frequency of the received data
stream (divided-by -10 or -20) must be within 200
ppm of the reference clock to insure reliable locking
of the receiver PLL.
QUAD SERIAL BACKPLANE DEVICE
October 10, 2000 / Revision D