ADV7174KCPZ Analog Devices Inc, ADV7174KCPZ Datasheet - Page 30

• Manufacturer Part Number: ADV7174KCPZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7174KCPZ

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LFCSP EP
• Pin Count: 40
• Lead Free Status / RoHS Status: Compliant

ADV7174/ADV7179
MODE REGISTER 2 (MR2)
Bits:
Address:
Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can
be read from as well as written to.
Table 11. MR2 Bit Description
Bit Name
Square Pixel Control
Genlock Control
Active Video Line Duration
Chrominance Control
Burst Control
Low Power Mode
Reserved
MR27–MR20
SR4–SR0 = 02H
RESERVED
MR27
MR27
Bit No.
MR20
MR22–MR21
MR23
MR24
MR25
MR26
MR27
MR26
LOW POWER MODE
0
1
MR26
DISABLE
ENABLE
MR25
0
1
CONTROL
ENABLE BURST
DISABLE BURST
Description
This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a
24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
These bits control the genlock feature of the ADV7174/ ADV7179. Setting MR21 to Logic 1
configures the SCRESET/RTC pin as an input. Setting MR22 to Logic 0 configures the
SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0
following a low-to-high transition on the SCRESET/RTC pin. Setting MR22 to Logic 1 configures
the SCRESET/RTC pin as a real-time control input.
This bit switches between two active video line durations. A 0 selects CCIR REC601 (720 pixels
PAL/NTSC), and a 1 selects ITU-R.BT470 standard for active video duration (710 pixels NTSC
and 702 pixels PAL).
This bit enables the color information to be switched on and off the video output.
This bit enables the burst information to be switched on and off the video output.
This bit enables the lower power mode of the ADV7174/ADV7179. This reduces the DAC
current by 45%.
A Logic 0 must be written to this bit.
BURST
MR25
MR24
0
1
CHROMINANCE
CONTROL
ENABLE COLOR
DISABLE COLOR
Figure 40. Mode Register 2
MR24
Rev. B | Page 30 of 52
MR23
0
1
ACTIVE VIDEO LINE
MR23
720 PIXELS
710 PIXELS/702 PIXELS
DURATION
MR22 MR21
x
0
1
GENLOCK CONTROL
MR22
0
1
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
MR21
MR20
SQUARE PIXEL
0
1
CONTROL
MR20
DISABLE
ENABLE