ADV7190KST Analog Devices Inc, ADV7190KST Datasheet
ADV7190KST
Specifications of ADV7190KST
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ADV7190KST Summary of contents
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... The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest available Macrovision version. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). SSAF is a trademark of Analog Devices Inc registered trademark of Philips Corporation ...
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ADV7190/ADV7191 CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPECIFICATIONS ( SPECIFICATIONS unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) 3 Integral Nonlinearity 3 Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V ...
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ADV7190/ADV7191–SPECIFICATIONS ( 3.3 V SPECIFICATIONS unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input ...
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V DYNAMIC–SPECIFICATIONS Parameter 3 Differential Gain 3 Differential Phase 3 SNR (Pedestal) 3 SNR (Ramp) Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma AM Noise ...
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ADV7190/ADV7191 5 V TIMING CHARACTERISTICS Parameter 2 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK ...
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V TIMING CHARACTERISTICS Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time, ...
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ADV7190/ADV7191 SDA SCL CLOCK HSYNC, CONTROL VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, VSYNC, CONTROL BLANK, O/PS CSO_HSO, VSO, CLAMP TTXREQ t 16 CLOCK TTX 4 CLOCK CYCLES ...
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... Analog output short circuit to any power supply or common can indefinite duration. Model Temperature Range ADV7190KST 0∞C to 70∞C ADV7191KST 0∞C to 70∞C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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ADV7190/ADV7191 Pin Input/ No. Mnemonic Output 1–16 P0–P15 I 17, 25, 29 38, 43, 54, 63 18, 24, 26, AGND G 33, 39, 42, 55, 64 HSYNC 19 I/O VSYNC 20 I/O BLANK 21 I/O 22 ALSB ...
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DETAILED DESCRIPTION OF FEATURES Clocking: Single 27 MHz Clock Required to Run the Device 4 Oversampling with Internal 54 MHz PLL Square Pixel Operation Advanced Power Management Programmable Video Control Features: Digital Noise Reduction Pedestal level Hue, Brightness, Contrast and ...
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ADV7190/ADV7191 Programmable gamma correction is also available. Figure 6 shows the response of different gamma values to a ramp signal. 300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES 250 SIGNAL OUTPUTS 200 0.3 0.5 150 ...
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Luma and Chroma Signals are added together to make up the Composite Video Signal. All timing signals are controlled. The YCrCb data is also used to generate RGB data with appropri- ate sync and blank levels. The YUV levels are ...
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ADV7190/ADV7191 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 9. NTSC Low-Pass Luma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 10. PAL ...
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FREQUENCY – MHz Figure 15. Extended SSAF and Programmable Attenuation, Showing Range 0 dB/– –2 –4 –6 –8 –10 – ...
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ADV7190/ADV7191 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 21. Chroma 1.3 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 22. ...
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FEATURES: FUNCTIONAL DESCRIPTION Brightness Detect This feature is used to monitor the average brightness of the incoming Y signal on a field-by-field basis. The information is 2 read from the I C and based on this information, the color saturation, ...
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ADV7190/ADV7191 In DNR Mode, if the absolute value of the filter output is smaller than the threshold assumed to be noise. A programmable amount (Coring Gain Control) of this noise signal will be sub- tracted from the original ...
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Vertical Blanking Data Insertion and BLANK Input It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not have line sync or pre-/post- equalization pulses (see Figures 34 to 45). This mode of ...
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ADV7190/ADV7191 When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV7190/ADV7191. Output timing signals are still suppressed at this stage. DACs are switched off and DACs ...
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COMPOSITE VIDEO e.g., VCR OR CABLE H/L TRANSITION COUNT START LOW RESERVED 128 13 RTC TIME SLOT: 01 NOTES PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7190/ADV7191. FSC DDS REGISTER BITS 21:0 PLUS ...
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ADV7190/ADV7191 Mode 0 (CCIR–656): Master Option (Timing Register 0 TR0 = The ADV7190/ADV7191 generates H, V, and F signals required for the SAV and EAV Time Codes in the CCIR656 standard. The ...
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ANALOG VIDEO Figure 36. Timing Mode 0 Data Transitions, Master Mode Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7190/ADV7191 accepts ...
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ADV7190/ADV7191 Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7190/ADV7191 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input ...
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DISPLAY 622 623 624 625 HSYNC BLANK VSYNC EVEN FIELD DISPLAY 309 310 311 312 HSYNC BLANK VSYNC ODD FIELD Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = ...
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ADV7190/ADV7191 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7190/ADV7191 accepts or generates Horizontal SYNC ...
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MPU PORT DESCRIPTION The ADV7190/ADV7191 supports a two-wire serial (I compatible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry information between any device connected to the bus. Each slave device is recognized by ...
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ADV7190/ADV7191 REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7190/ADV7191 with the exception of the Subaddress Regis- ters, which are write-only registers. The Subaddress Register determines which register the next read or ...
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MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) Figure 50 shows the various operations under the control of Mode Register 0. MR0 BIT DESCRIPTION Output Video Standard Selection (MR00–MR01) These bits are used to set up the encoder mode. ...
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ADV7190/ADV7191 MODE REGISTER 2 MR2 (MR27–MR20) (Address (SR4–SR0) = 02H) Mode Register 8-bit-wide register. Figure 52 shows the various operations under the control of Mode Register. MR2 BIT DESCRIPTION— RGB/YUV Control (MR20) This bit enables the output ...
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MODE REGISTER 3 MR3 (MR37–MR30) (Address (SR4–SR0) = 03H) Mode Register 8-bit-wide register. Figure 53 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION Revision Code (MR30–MR31) This bit is read only ...
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ADV7190/ADV7191 MR47 COLOR BAR CONTROL MR46 0 1 INTERLACED MODE CONTROL MR47 0 INTERLACED 1 NONINTERLACED Interlaced Mode Control (MR47) This bit is used to setup the output to interlaced or noninter- laced mode. MODE REGISTER 5 MR5 (MR57–MR50) (Address ...
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MODE REGISTER 6 MR6 (MR67–MR60) (ADDRESS (SR4–SR0) = 06H) Mode Register 8-bit-wide register. Figure 56 shows the various operations under the control of Mode Register 6. MR6 BIT DESCRIPTION Power-Up Sleep Mode Control (MR60) After RESET is ...
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ADV7190/ADV7191 Reserved (MR76) A Logic 0 must be written to this bit. CLAMP/VSO Select (MR77) This bit is used to select the functionality of Pin 51 selects CLAMP as the output signal selects VSO output. MODE ...
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TIMING REGISTER 0 (TR07–TR00) (Address (SR4–SR0) = 0AH) Figure 60 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. TR0 BIT DESCRIPTION Master/Slave Control (TR00) This bit ...
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ADV7190/ADV7191 TR17 TR16 HSYNC TO PIXEL DATA ADJUST TR17 TR16 TIMING MODE 1 (MASTER/PAL) HSYNC VSYNC SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC31–FSC0) (Address (SR4–SR0) = ...
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NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0) (Subaddress (SR4–SR0) = 15–18H) These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. ...
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ADV7190/ADV7191 CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address (SR4–SR0) = 1AH) CGMS_WSS Register 8-bit-wide register. Figure 70 shows the operations under control of this register. C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W10–C/W15) These bit locations are shared by CGMS ...
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HUE ADJUST CONTROL REGISTER (HCR) (Address (SR5–SR0) = 20H hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. Figure 74 shows the operation under control of this register. HCR7 ...
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ADV7190/ADV7191 SHARPNESS CONTROL REGISTER (PR) (Address (SR5–SR0) = 22H) The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to select a desired filter response. Figure 76 ...
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DNR17 BLOCK SIZE CONTROL DNR17 0 8 PIXELS 1 16 PIXELS DNR2 BIT DESCRIPTION DNR Input Select (DNR20–DNR22) Three bits are assigned to select the filter that is applied to the incoming Y data. The signal that lies in the ...
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ADV7190/ADV7191 DNR27 DNR DNR DNR DNR • • • • • • GAMMA CORRECTION REGISTERS 0–13 (GAMMA CORRECTION 0–13) (Address (SR5–SR0) = 26H–32H) The Gamma Correction ...
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BRIGHTNESS DETECT REGISTER (Address (SR5–SR0) = 34H Brightness Detect Register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of the incoming video data on a field-by-field basis. The brightness 2 ...
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ADV7190/ADV7191 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7190/ADV7191 is a highly integrated circuit contain- ing both precision analog and high-speed digital circuitry. It has been designed to minimize interference effects on the integ- rity of the analog circuitry by the ...
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AA AA 0.1 F 0.1 F UNUSED INPUTS SHOULD BE GROUNDED 4.7k 4 27MHz CLOCK 4.7k (SAME CLOCK AS USED BY MPEG2 DECODER) REV. B APPENDIX ...
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ADV7190/ADV7191 The ADV7190/ADV7191 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed ...
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COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7190/ADV7191 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether ...
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ADV7190/ADV7191 The ADV7190/ADV7191 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7190/ADV7191 is configured in PAL mode. The WSS data is 14-bits long, the ...
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Time the time needed by the ADV7190/ADV7191 to PD interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears t SYNTTXOUT leading edge of the horizontal signal. Time, TTX ...
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ADV7190/ADV7191 If an output filter is required for the CVBS, YUV, Chroma, and RGB outputs of the ADV7190/ADV7191, the filter in Figure 94 can be used in 2¥ Oversampling Mode. Figure 96 shows a filter that can be used in ...
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External buffering is needed on the ADV7190/ADV7191 DAC outputs. The configuration in Figure 99 is recommended. When calculating absolute output full-scale current and voltage use the following equations: ¥ OUT OUT LOAD ¥ K)/ ...
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ADV7190/ADV7191 The ADV7190/ADV7191 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. NTSC (F = 3.5795454 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 ...
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PAL 4.43361875 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register 7 ...
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ADV7190/ADV7191 PAL 3.57561149 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register ...
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POWER-ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode ...
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ADV7190/ADV7191 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 963.8mV 286mV (p-p) 650mV 335.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) Figure ...
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IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 307mV (p-p) 650mV 283mV 0mV 100 IRE 0 IRE –40 IRE REV. B NTSC WAVEFORMS (WITHOUT PEDESTAL) Figure 105. NTSC Composite Video Levels Figure 106. ...
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ADV7190/ADV7191 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 990mV 300mV (p-p) 650mV 318mV 0mV 1050.2mV 351.8mV 51mV PAL WAVEFORMS Figure 109. PAL Composite Video Levels Figure 110. PAL Luma Video Levels 672mV (p-p) Figure 111. PAL Chroma Video Levels Figure ...
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BETACAM LEVEL 0mV 171mV 334mV 505mV Figure 113. NTSC 100% Color Bars, No Pedestal U Levels 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV Figure 114. NTSC 100% Color Bars with Pedestal U Levels 232mV SMPTE LEVEL 118mV ...
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ADV7190/ADV7191 0.6 0.4 0.2 0.0 0.2 L608 0.0 10.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.5 0.0 0.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL ...
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L575 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s Figure 121. 100/0/75/0 PAL Color Bars Chrominance 100.0 0.5 50.0 0.0 –50.0 0.0 APL = 44.6% 525 LINE NTSC ...
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ADV7190/ADV7191 100.0 0.6 0.4 50.0 0.2 0.0 0.0 –0.2 10.0 NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC SLOW CLAMP TO 0. 6.72 s Figure 123. 100/7.5/75/7.5 NTSC Color Bars Luminance 0.4 50.0 0.2 0.0 –0.2 –50.0 ...
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PARADE SMPTE/EBU PAL mV Y(A) 700 600 500 400 300 200 100 0 –100 –200 –300 mV GREEN (A) 700 600 500 400 300 200 100 0 –100 –200 –300 REV Pb(B) mV Pr(C) 250 250 200 200 ...
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ADV7190/ADV7191 COLOR BAR (NTSC) FIELD = 1 LINE = 21 LUMINANCE LEVEL (IRE) 99.6 69.0 100 50 0 GRAY YELLOW CHROMINANCE LEVEL (IRE) 0.0 62.1 100 50 0 GRAY YELLOW CHROMINANCE PHASE (DEGREE) 167.3 400 200 0 GRAY YELLOW AVERAGE ...
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DG DP (NTSC) WFM FIELD = 1, LINE = 21 DIIFFERENTIAL GAIN (PERCENT) MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27 0.00 0.21 0.02 0.07 2.5 1.5 0.5 –0.5 –1.5 –2 ...
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ADV7190/ADV7191 CHROMINANCE NONLINEARITY(NTSC) WFM FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.5 0 –10 20IRE 40IRE CHROMINANCE PHASE ERROR (DEGREE) –0.0 0 –5 20IRE 40IRE CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714mV) 0.0 0.1 ...
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NOISE SPECTRUM (NTSC) WFM FIELD = 2, LINE = 223 AMPLITUDE (0dB = 714mV p-p) BANDWIDTH 10kHz TO FULL 20 0 –20 –40 –60 –80 –100 MHz Figure 137. NTSC Noise Spectrum: Pedestal NOISE SPECTRUM (NTSC) WFM ...
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ADV7190/ADV7191 APL = 39. SOUND IN SYNC OFF APL = 45.1% YI –Q SETUP 7.5% APPENDIX 10 VECTOR PLOTS 75% 100 Figure 141. PAL Vector Plot R-Y ...
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SEATING 0.004 (0.102) MAX LEAD COPLANARITY REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 64-Lead Quad Flatpack [LQFP] (ST-64) 0.640 (16.25) 0.063 (1.60) 0.630 (16.00) SQ MAX 0.620 (15.75 ...
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ADV7190/ADV7191 Revision History Location 5/02—Data Sheet changed from REV REV. B. Added Figure 46b . . . . . . . . . . . . . . . . . . . . . . . . ...
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