ADV7170KSUZ Analog Devices Inc, ADV7170KSUZ Datasheet - Page 35

• Manufacturer Part Number: ADV7170KSUZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7170KSUZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: TQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

SUBCARRIER
SUBCARRIER
SUBCARRIER
SUBCARRIER FREQUENCY REGISTERS 0 TO 3
(FSC3 TO FSC0)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using
the following equation, rounded to the nearest integer:
For example, in NTSC mode,
Note that on power-up, F
as derived above is recommended.
Program as follows:
FSC Register 0: 1FH
FSC Register 2: 7CH
FSC Register 3: F0H
FSC Register 4: 21H
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER
Subcarrier
(Address [SR4 to SR00] = 09H to 0CH)
FREQUENCY
FREQUENCY
FREQUENCY
No
FREQUENCY
.
of
REG 0
REG 1
REG 2
REG 3
Subcarrier
No
Frequency
.
FSC15
FSC23
FSC31
of
FSC7
27
Figure 45. Subcarrier Frequency Register
MHz
FSC14 FSC13
FSC22 FSC21
Frequency
FSC30 FSC29
FSC6
V
alue
Clock
FSC5
SC
TR17 TR16
FIELD/VSYNC
=
Register 0 is set to 16h. A value of 1F
TIMING MODE 1 (MASTER/PAL)
0
0
1
1
Cycles
Values
HSYNC TO PIXEL
227
1716
DATA ADJUST
FSC12
FSC20
FSC28
FSC4
HSYNC
5 .
0
1
0
1
TR17
×
in
in
0 × T
1 × T
2 × T
3 × T
FSC19
2
FSC11
FSC27
FSC3
32
One
One
PCLK
PCLK
PCLK
PCLK
=
TR16
569408542
Video
Line
FSC10
FSC18
T
FSC26
FSC2
LINE 1
B
T
A
TR15 TR14
TR15 TR14
of
Line
0
0
1
1
x
x
RISING EDGE DELAY
FSC17
FSC25
FSC1
FSC9
Video
HSYNC TO FIELD
(MODE 2 ONLY)
(MODE 1 ONLY)
VSYNC WIDTH
TR15
d
0
1
0
1
0
1
=
FSC16
FSC24
FSC0
FSC8
Line
21
Figure 44. Timing Register 1
1 × T
4 × T
16 × T
128 × T
T
T
F
B
B
Rev. C | Page 35 of 64
T
07
TR14
+ 32μs
PCLK
PCLK
C
×
PCLK
PCLK
C
2
1
32
Fh
TR13 TR12
FIELD/VSYNC DELAY
0
0
1
1
TR13
SUBCARRIER PHASE REGISTERS (FP7 TO FP0)
(Address [SR4 to SR0] = 0DH)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
CLOSED CAPTIONING EVEN FIELD DATA
REGISTER 1 TO 0 (CED15 TO CED0)
(Address [SR4–SR0] = 0E to 0FH)
These 8-bit-wide registers are used to set up the closed
captioning extended data bytes on even fields. Figure 46
shows how the high and low bytes are set up in the registers.
CLOSED CAPTIONING ODD FIELD DATA
REGISTERS 1 TO 0 (CCD15 TO CCD0)
(Subaddress [SR4 to SR0] = 10H to 11H)
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
HSYNC TO
BYTE 0
BYTE 0
0
1
0
1
BYTE 1
BYTE 1
TR12
0 × T
4 × T
8 × T
16 × T
T
T
CED7
CCD7
B
PCLK
PCLK
PCLK
C
Figure 46. Closed Captioning Extended Data Register
PCLK
LINE 313
CED15
CCD15
Figure 47. Closed Captioning Data Register
CED6
CCD6
TR11
TR11 TR10
CED14 CED13
CCD14 CCD13
0
0
1
1
HSYNC WIDTH
CED5
CCD5
0
1
0
1
LINE 314
TR10
1 × T
4 × T
16 × T
128 × T
CED4
CCD4
T
CED12
CCD12
PCLK
PCLK
A
PCLK
PCLK
ADV7170/ADV7171
CED3
CCD3
CED11
CCD11
CED2
CCD2
CED10
CCD10
CED1
CCD1
CED9
CCD9
CED0
CCD0
CED8
CCD8