ADV7176AKS Analog Devices Inc, ADV7176AKS Datasheet - Page 18

• Manufacturer Part Number: ADV7176AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKS

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

ADV7175A/ADV7176A
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7175A/ADV7176A can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge
following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the
HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
HSYNC
BLANK
HSYNC
VSYNC
BLANK
VSYNC
522
DISPLAY
260
DISPLAY
523
261
HSYNC
BLANK
FIELD
PIXEL
DATA
524
262
525
263
NTSC = 16 * CLOCK/2
PAL = 12 * CLOCK/2
1
264
EVEN FIELD
ODD FIELD
2
265
3
266
4
267
5
VERTICAL BLANK
268
VERTICAL BLANK
6
269
EVEN FIELD
ODD FIELD
7
270
8
271
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
9
272
10
273
Cb
11
274
Y
Cr
Y
20
283
21
284
DISPLAY
DISPLAY
22
285