LM1267NA National Semiconductor, LM1267NA Datasheet - Page 18

• Manufacturer Part Number: LM1267NA
• Manufacturer: National Semiconductor

Specifications of LM1267NA

• Power Supply Requirement: Single
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Pin Count: 24
• Package Type: MDIP
• Lead Free Status / RoHS Status: Not Compliant

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R Gain
Control
B Gain
Control
G Gain
Control
Contrast
Cont.
DAC1
DAC2
DAC3
DAC4
DC Offset/
OSD Cont.
Global
Control
Increment
Mode
Clamp/BW
Software
Reset
I
I
Slave Address of the LM1267 is DCh when writing to the registers and DD when reading from the registers.
Pre-Amp Interface Registers
Red Channel Gain Control Register (I
Register name: R Gain Control (00h)
Bits 6–0: Red Channel Gain Control. These seven bits de-
Bit 7:
Blue Channel Gain Control Register (I
Register name: B Gain Control (01h)
Bits 6–0: Blue Channel Gain Control. These seven bits
Bit 7:
Green Channel Gain Control Register (I
Register name: G Gain Control (02h)
Bits 6–0: Green Channel Gain Control. These seven bits
Bit 7:
2
2
Bit 7
RSV
Bit 7
RSV
Bit 7
RSV
Register
C IC ADDRESS
C Interface Registers
GG6
RG6
BG6
termine the gain for the Red Channel.
Reserved.
determine the gain for the Blue Channel.
Reserved.
determine the gain for the Green Channel.
Reserved.
GG5
RG5
BG5
dress
Ad-
0A
0B
0F
00
01
02
03
04
05
06
07
08
09
GG4
RG4
BG4
fault
De-
60h
60h
60h
60h
80h
80h
80h
80h
15h
00h
00h
04h
00h
RG3
GG3
BG3
LM1267 Pre-Amp Interface Registers (all numbers in Hex)
RG2
BG2
GG2
2
2
C address 00h)
C address 01h)
2
X
X
X
X
X
X
X
X
X
C address 02h)
GG1
RG1
BG1
Bit 0
GG0
Bit 0
RG0
BG0
Bit 0
X
X
X
X
X
18
O
X
X
X
X
Contrast Control Register (I
Register name: Contrast Control (03h)
Bits 6–0: Contrast Control. These seven bits vary the gain
Bit 7:
DAC Interface Register Definitions
DAC 1 Register (I
Register name: DAC 1 (04h)
Bits 7–0: DAC 1. These eight bits determine the output
DAC 2 Register (I
Register name: DAC 2 (05h)
Bits 7–0: DAC 2. These eight bits determine the output
DAC 3 Register (I
Bit 7
D1–7 D1–6 D1–5 D1–4 D1–3 D1–2 D1–1 D1–0
Bit 7
D2–7 D2–6 D2–5 D2–4 D2–3 D2–2 D2–1 D2–0
Bit 7
RSV
DCF4
CG6
X
X
X
of all three channels.
Reserved.
voltage of DAC 1.
voltage of DAC 2.
OSD_Cont.
DAC 1[7:0]
DAC 2[7:0]
DAC 3[7:0]
DAC 4[7:0]
Format
[1:0]
CG5
DCF1–3
2
2
2
CLMP
C address 04h)
C address 05h)
C address 06h)
Contrast [6:0]
X
X
G Gain [6:0]
R Gain [6:0]
B Gain [6:0]
CG4
2
C address 03h)
CG3
O
X
X
BANDWIDTH[2:0]
DC_Offset [2:0]
CG2
PS
O
X
CG1
Bit 0
CG0
SRST
Bit 0
Bit 0
INCR
BV