LM1207AN National Semiconductor, LM1207AN Datasheet - Page 11

• Manufacturer Part Number: LM1207AN
• Manufacturer: National Semiconductor

Specifications of LM1207AN

• Power Supply Requirement: Single
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Figure 6 is a detailed block diagram of the green channel of
the LM1205A/LM1207A along with the recommended exter-
nal components. The IC pin numbers are circled and all ex-
ternal components are shown outside the dashed line. The
other two video channels are identical to the green channel,
only the numbers to the pins unique to each channel are dif-
ferent. The input video is normally terminated into 75 . The
termination resistor depends on the impedance of the coax
cable being used, 75
used in video applications. The video signal is AC coupled
through a 10 µF capacitor to the input, pin 6. There is no
standard for the DC level of a video signal, therefore the sig-
nal must be AC coupled to the LM1205A/LM1207A. Internal
to the LM1205A/LM1207A is a 2.8V reference, giving the in-
put video an offset voltage of 2.8V. This voltage was selected
to give the input video enough DC offset to guarantee that
the lowest voltage of the video signal at pin 6 is far enough
above ground to keep the LM1205A/LM1207A in the active
region. The 200
and for current limiting during any voltage surge that may oc-
cur at the input, driving pin 6 above V
nal is buffered by −A1. In this circuit description an inverting
amplifier is shown with a “−” (minus sign) in front of the am-
plifier designation. The output of −A1 goes to the contrast
and drive attenuator sections.
The contrast and drive control sections are virtually identical.
Both sections take a 0V to 4V input voltage, 4V giving the
maximum gain for either the contrast or the drive. This is a
high impedance input, allowing for an easy interface to 5V
DACs. One may also use 100k potentiometers with no deg-
radation in performance. The contrast control section is com-
mon to all three channels. It converts the input voltage at pin
12 to a couple of internal DC voltages that control the gain of
the contrast attenuator. Referring to the Attenuation vs Con-
trast Voltage under typical performance characteristics note
that a 4V control voltage results in no attenuation of the
video signal. A 0.25V control voltage results in an attenuation
of 40 dB. Again note that these internal control voltages are
common to all three channels. To minimize crosstalk, these
voltages go to pins 1 and 2. Minimizing crosstalk is done by
adding the RC network shown in the block diagram
( Figure 6 ).
The 0V to 4V drive control signal comes in on pin 18. Each
channel has its own drive section, therefore the crosstalk
compensation needed for the contrast control voltages is not
required for the drive control, thus no external pins for the
drive control. The drive attenuator gives an attenuation
range from 0 dB to −6 dB. A small gain adjustment range for
the drive attenuator is desirable and intentionally designed
because the drive is used only to balance the overall gain of
each color channel, giving the correct color temperature on
the CRT.
The output of the drive attenuator stage goes to A2, the am-
plifier in the DC restoration section. The video signal goes to
the non-inverting input of A2. The inverting side of A2 goes to
the output of gm1, the clamp comparator, and the clamp ca-
pacitor at pin 8.
resistor at the input is for ESD protection
being the most common impedance
CC
. The input video sig-
11
During the back porch period of the video signal a negative
going clamp pulse from pin 14 is applied to the clamp com-
parator, turning on the comparator. This period is where the
black level of the video signal at the output of the LM1205A/
LM1207A is compared to the desired black level which is set
at pin 19. Figure 7 shows the timing of the clamp pulse rela-
tive to the video signal. The clamp capacitor is charged or
discharged by gm1, generating the correction voltage
needed at the inverting input of A2 to set the video output to
the correct DC level. Removing the clamp pulse turns off
gm1 with the correction voltage being maintained by the
clamp capacitor during active video. Both the clamp pulse
and the blank pulse at pin 13 are TTL voltage levels.
There are actually two output sections, −A3 and −A4. Both
sections have been designed to be identical, except −A4 has
more current drive capability. The output transistor shown is
part of −A4, but has been shown separately so the user
knows the configuration of the output stage. −A3 does not go
to the outside world, it is used for feeding back the video sig-
nal for DC restoration. Its output goes directly to the inverting
input of the clamp comparator via the voltage divider formed
by the 500
output as −A3 and will temperature track due to the similar
design of the two output stages. However, the current at the
output of −A4 will be ten times the current at the output of
−A3. To balance both outputs, a load resistance of 390
needs to be connected from pin 20, the green video output
pin, to ground. Another input to −A4 is the blank pulse. When
a negative going blank pulse is applied to pin 13, the output
of the LM1205A/LM1207A is driven to less than 0.1V above
ground. Using the timing shown in Figure 7 for the blank
pulse, the output of the LM1205A/LM1207A will be less than
0.1V during the inactive portion of the video signal. This is a
“blacker than black” condition, blanking the CRT at the cath-
odes. By using the blank function of the LM1205A/LM1207A
no grid blanking is necessary. Note that the DC restoration is
done by feeding back the video signal from −A3, but blank-
ing is done at −A4. By using the two output stages, blanking
can be done at the CRT cathodes, and at the same time ac-
tivate the DC restoration loop.
V
pins are all internally connected. For proper operation of the
LM1205A/LM1207A it is necessary to connect all the V
pins to the input power to the PCB and bypass each pin with
a 0.1 µF capacitor. V
for the three output stages. This is a separate power input
from V
two different power inputs. There must be a connection on
the PCB between V
bypassed by a parallel connection of a 10 µF and 0.1 µF ca-
pacitors. The ground connections for the LM1205A/
LM1207A are at pins 7, 21, and 24. All three ground pins are
internally connected, and these pins must also be connected
externally to a good ground plane for proper operation of the
LM1205A/LM1207A.
CC1
goes to pins 3, 11, and 25 (see Figure 1 ). These three
CC1
, there are no internal connections between the
and 4k resistors. −A4 will be close to the same
CC1
CC2
and V
is the input power at pins 22 and 23
CC2
. Pins 22 and 23 must be
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CC1