STAC9750XXTAEC1X IDT, Integrated Device Technology Inc, STAC9750XXTAEC1X Datasheet - Page 30

• Manufacturer Part Number: STAC9750XXTAEC1X
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of STAC9750XXTAEC1X

• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
5.3.
Waking up the AC-Link
The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the
STAC9750/9751 to this low power mode.
Once the STAC9750/9751 has halted BIT_CLK, there are only two ways to “wake up” the AC-Link.
Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a “Cold
AC'97 Reset”, and a “Warm AC'97 Reset”. The current power down state would ultimately dictate
which form of reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset register) is
performed, wherein the AC'97 registers are initialized to their default values, registers are required to
keep state during all power down modes. Once powered down, re-activation of the AC-Link via
re-assertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the
frame in which the power down was triggered. When AC-Link powers up it indicates readiness via
the CODEC Ready bit (input slot 0, bit 15).
Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time, and
then bringing RESET# back HIGH. The reset occurs on the rising edge when RESET# is deas-
serted. By asserting and deasserting RESET#, BIT_CLK and SDATA_IN will be activated, or re-acti-
vated as the case may be, and all STAC9750/9751 control registers will be initialized to their default
power-on-reset values.
Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9750/9751
register values. A warm reset is signaled by driving SYNC high for a minimum of 1 µs in the absence
of BIT_CLK.
Note: RESET# is an asynchronous input. (# denotes active low)
Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of BIT_CLK,
SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9750/
9751.
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STAC9750/9751
PC AUDIO
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