AD73411BB-40 Analog Devices Inc, AD73411BB-40 Datasheet - Page 10

• Manufacturer Part Number: AD73411BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73411BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

The AFE is configured as a single I/O channel (similar to that of
the discrete AD73311L; refer to the AD73311L data sheet for
more details) having a 16-bit sigma-delta-based ADC and DAC.
Both ADC and DAC share a common reference whose nominal
value is 1.2 V. Figure 2 shows a block diagram of the AFE sec-
tion of the AD73411. It shows an ADC and DAC as well as a
common reference. Communication to both channels is handled
by the SPORT2 block which interfaces to either SPORT0 or
SPORT1 of the DSP section.
The I/O channel features fully differential inputs and outputs.
The input section allows direct connection to the internal Pro-
grammable Gain Amplifier at the input of the sigma-delta
ADC section. The input section also features programmable differ-
ential channel inversion and configuration of the differential
input as two separate single-ended inputs. The ADC features a
second order sigma-delta modulator which samples at MCLK/8.
Its bitstream output is filtered and decimated by a Sinc-cubed
decimator to provide a sample rate selectable from 64 kHz,
32 kHz, 16 kHz or 8 kHz (based on an MCLK of 16.384 MHz).
The DAC channel features a Sinc-cubed interpolator which
increases the sample rate from the selected rate to the digital
sigma-delta modulator rate of MCLK/8. The digital sigma-delta
modulator’s output bitstream is fed to a single-bit DAC whose
output is reconstructed/filtered by two stages of low-pass filtering
(switched capacitor and continuous time) before being applied
to the differential output driver.
FUNCTIONAL DESCRIPTION
Encoder Channel
The encoder channel consists of an input configuration block, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input anti-
alias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Input Configuration Block
The input configuration block consists of a multiplexing arrange-
ment that allows selection of various input configurations. This
includes ADC input selection from either the VINP, VINN pins
AD73411
REFOUT
REFCAP
VOUTN
VOUTP
VINP
VINN
+6/–15dB
SINGLE-ENDED
PGA
LOOPBACK/
ANALOG
ENABLE
LOW-PASS FILTER
REFERENCE
AVDD1
AGND1
CONTINUOUS
TIME
0/38dB
PGA
AVDD2
AGND2
LOW-PASS FILTER
CAPACITOR
SWITCHED-
SIGMA-DELTA
MODULATOR
ANALOG
or from the DAC output via the Analog Loop-Back (ALB)
arrangement. Differential inputs can be inverted and it is also
possible to use the device in single-ended mode, which allows
the option of using the VINP, VINN pins as two separate
single-ended inputs, either of which can be selected under soft-
ware control.
Programmable Gain Amplifier
The encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modulator.
The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table I, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in Control Register D.
IGS2
0
0
0
0
1
1
1
1
ADC
The ADC consists of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decima-
tion filter reduces the sample rate and increases the resolution.
1-BIT
DAC
AD73411
Table I. PGA Settings for the Encoder Channel
SIGMA-DELTA
MODULATOR
DIGITAL
IGS1
0
0
1
1
0
0
1
1
DVDD
DGND
DECIMATOR
INTERPOLATOR
IGS0
0
1
0
1
0
1
0
1
SERIAL
PORT
I/O
Gain (dB)
0
6
12
18
20
26
32
38
SDI
SDIFS
SCLK
SDO
SDOFS
SE
MCLK
RESET