AD9100JD Analog Devices Inc, AD9100JD Datasheet - Page 7

• Manufacturer Part Number: AD9100JD
• Manufacturer: Analog Devices Inc

Specifications of AD9100JD

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

REV. A
While a single ground plane is recommended, the analog signal
and differential ECL clock ground currents follow a narrow path
directly under their common voltage signal line. To reduce re-
flections, especially when terminations are used for transmission
line efficiency, the clock, V
ground paths should not cross each other; if they do, unwanted
coupling can result.
High current ground transients via the high frequency decou-
pling capacitors can also cause unwanted coupling to the V
and V
should be kept as far as possible from the power supply decou-
pling capacitors to minimize feedthrough.
Using Sockets
Pin sockets (P/N 6-330808-3 from AMP) should be used if the
device can not be soldered directly to the PCB. High profile or
wire wrap type sockets will dramatically reduce the dynamic
performance of the device in addition to increasing the case-to-
ambient thermal resistance.
Driving the Encode Clock
The AD9100 requires a differential ECL clock command. Due
to the high gain bandwidth of the AD9100 internal switch, the
input clock should have a slew rate of at least 100 V/ s.
To obtain maximum signal to noise performance, especially at
high analog input frequencies, a low jitter clock source is
required. The AD9100 clock can be driven by an AD96685, an
ultrahigh speed ECL comparator with very low jitter.
V
NOTE:
CONNECT TO W1 FOR TTL CLOCK SIGNALS;
CONNECT TO W2 FOR GROUND-REFERENCED SIGNALS.
BUFF
J3
Figure 2. AD9100/PCB Evaluation Board Diagram
OUT
CLK
V
IN
8
current loops. Therefore, these analog terminations
AD9620
J1
V
19
OUT
50
R
IN
J2
4
TP1
10µF
C14
+5V
150
C1
Clock/ Clock Input Stage
C2
C4
C3
CLOCK
–5.2V
IN
–V
R
2k
W1
W2
L
5
S
R
S
1k
100
J5
68
R1
47
R2
IN
R3
, and V
10
4
9
1
2
3
5
6
7
8
2
3
+V
AD96685
9,10
1
AD9100
S
(DIP)
DUT
OUT
–V
J6
5
4
S
LE
7
8
–5.2V
C10
signals and respective
C9
Q
Q
1k
11
20
19
18
17
16
15
14
13
12
150
J7
+V
S
18
C5
C6
C7
C8
CLK
C13
10µF
TP3
510
510
IN
R4
R5
–5.2V
–7–
Driving the Analog Input
Special care must be taken to ensure that the analog input signal
is not compromised before it reaches the AD9100. To obtain
maximum signal to noise performance, a very low phase noise
analog source is required. In addition, input filtering and/or a
low harmonic signal source is necessary to maximize the
spurious free dynamic range. Any required filtering should be
done close to the AD9100 and away from any digital lines.
Overdriving the Analog Input
The AD9100 has input clamps that prevent hard saturation of
the output buffer, thereby providing fast overvoltage recovery
when the analog input transitions to the linear region ( 2 V).
The clamps are set internally at 2.3 V and cannot be altered by
the user. The output settles to 0.1% of its value 21 ns after the
overvoltage condition is alleviated. When the analog input is
outside the linear region, the analog output will be at either
+2.2 V or –2.2 V.
Matching the AD9100 to A/D Encoders
The AD9100’s analog output level may have to be offset or
amplified to match the full-scale range of a given A/D converter.
This can generally be accomplished by inserting an amplifier
after the AD9100. For example, the AD671 is a 12-bit 500 ns
monolithic ADC encoder that requires a 0 to +5 V full-scale
analog input. An AD84X series amplifier could be used to
condition the AD9100 output to match the full-scale range of
the AD671.
Ultralow Distortion/Low Resistive Load Applications
When driving low resistive loads or when the widest possible
spurious free dynamic range is required, system performance
can be improved by isolating the load from the AD9100. (See
Figure 3.) The AD9620 low distortion closed-loop buffer
amplifier has an input resistance of 800 k and generates
harmonics that are less than those generated by the AD9100.
Other buffers should not be considered if their harmonics are
not lower than those of the AD9100.
Direct IF Conversion
The AD9100 can be used to sample super-Nyquist signals,
making wide dynamic range direct IF to digital conversion
practical. By reducing the analog input level to the track and
hold, distortion due to the AD9100 can be minimized. As the
input level is reduced, the gain in the output amplifier (see
Figure 4) must be increased to match the full scale level of the
subsequent analog to digital converter.
ANALOG
INPUT
Figure 3. Using AD9620 as Isolation Amplifier
AD9100
AD9620
AD9100
INTO LOW
RESISTIVE
LOAD