MC34911G5AC Freescale, MC34911G5AC Datasheet - Page 45

• Manufacturer Part Number: MC34911G5AC
• Manufacturer: Freescale

Specifications of MC34911G5AC

• Turn Off Delay Time: 10us
• Number Of Drivers: 2
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

WDOFF - Watchdog Off
to Ground and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
WDWO - Watchdog Window Open
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
Analog Multiplexer Control Register - MUXCR
the divider ration for the Lx input divider.
LXDS - Lx Analog Input Divider Select
analog inputs. Voltage is internally clamped to VDD.
MXx - Analog Multiplexer Input Select
multiplexed to the ADOUT0 pin according to
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Table 28. Analog Multiplexer Channel Select
Analog Integrated Circuit Device Data
Freescale Semiconductor
MX2
This read-only bit signals that the watchdog pin connected
1 = Watchdog is disabled
0 = Watchdog is enabled
This read-only bit signals when the watchdog window is
1 = Watchdog window open
0 = Watchdog window closed
This register controls the analog multiplexer and selects
This write-only bit selects the resistor divider for the Lx
0 = Lx Analog divider: 1
1 = Lx Analog divider: 3.6 (typ.)
These write-only bits selects which analog input is
When disabled or when in Stop or Sleep mode, the output
0
0
0
0
1
1
1
1
Table 27. Analog Multiplexer Control Register -$C
Reset Condition
Reset Value
Write
MX1
0
0
1
1
0
0
1
1
MX0
LXDS
POR
C3
0
1
0
1
0
1
0
1
1
POR, Reset mode or ext_reset
MX2
C2
0
Die Temperature Sensor
VSENSE input
Reserved
Reserved
Reserved
Meaning
Disabled
MX1
L1 input
L2 input
C1
0
Table
MX0
C0
0
28.
Configuration Register - CFR
CYSX8 - Cyclic Sense Timing x 8.
Wake-up period as shown in
Interrupt Mask Register - IMR
sources. No interrupt will be generated to the MCU and no
flag will be set in the ISR register. The 5.0V Regulator over-
temperature prewarning interrupt and Under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
HSM - High Side Interrupt Mask
the high side block.
LSM - Low Side Interrupt Mask
the low side block.
LINM - LIN Interrupts Mask
the LIN block.
Table 29. Configuration Register - $D
Condition
This register controls the cyclic sense timing multiplier.
This write-only bit influences the cyclic sense and Forced
1 = Multiplier enabled
0 = None
This register allows masking of some of the interrupt
Writing to the IMR will return the ISR.
This write-only bit enables/disables interrupts generated in
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
Reset
Value
Reset
Write
Table 30. Interrupt Mask Register - $E
Reset Condition
Reset Value
Write
POR, Reset mode
or ext_reset
C3
0
0
HSM
C3
1
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATIONS
Table
CYSX8
POR
C2
LSM
0
C2
1
25.
POR
LINM
C1
POR
1
C1
0
0
VMM
C0
1
POR
C0
0
0
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