DS90CF364AMTDX National Semiconductor, DS90CF364AMTDX Datasheet - Page 11
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DS90CF364AMTDX
Manufacturer Part Number
DS90CF364AMTDX
Description
Manufacturer
National Semiconductor
Datasheet
1.DS90CF364AMTDX.pdf
(14 pages)
Specifications of DS90CF364AMTDX
Number Of Elements
3
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Differential Input High Threshold Voltage
100mV
Diff. Input Low Threshold Volt
-100mV
Output Type
Flat Panel Display
Operating Temp Range
-10C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
TSSOP
Number Of Receivers
3
Number Of Drivers
21
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS90CF364AMTDX
Manufacturer:
NS/国半
Quantity:
20 000
Company:
Part Number:
DS90CF364AMTDX/NOPB
Manufacturer:
NS/TI
Quantity:
120
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
CC
CC
DS90CF384A Pin Descriptions — 56L TSSOP Package — 24-Bit FPD Link
Receiver
DS90CF364A Pin Descriptions — 48L TSSOP Package — 18-Bit FPD Link
Receiver
Pin Name
Pin Name
CC
CC
CC
CC
I/O No.
I/O No.
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
28
3
3
1
1
1
1
4
5
1
2
1
3
4
4
1
1
1
1
4
5
1
2
1
3
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
11
Description
Description
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