DS90C363BMT National Semiconductor, DS90C363BMT Datasheet - Page 4

• Manufacturer Part Number: DS90C363BMT
• Manufacturer: National Semiconductor

Specifications of DS90C363BMT

• Number Of Elements: 3
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Flat Panel Display
• Differential Output Voltage: 450mV
• Transmission Data Rate: 455Mbps
• Power Dissipation: 1.98W
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TSSOP
• Number Of Receivers: 21
• Number Of Drivers: 3
• Lead Free Status / RoHS Status: Not Compliant

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TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
SSCG
TPLLS
TPDD
Symbol
Transmitter Switching Characteristics
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
AC Timing Diagrams
Over recommended operating supply and temperature ranges unless otherwise specified
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN (Figure 6 )
TxIN Hold to TxCLK IN (Figure 6 )
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle input
clock is assumed, T
and 25MHz for ” Max ”, V
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle input
clock is assumed, T
and 25MHz for ” Max ”, V
Spread Spectrum Clock support; Modulation frequency with a
linear profile (Note 6)
Transmitter Phase Lock Loop Set (Figure 8 )
Transmitter Power Down Delay (Figure 10 )
A
A
= −10˚C, and 65MHz for ” Min ”, T
= −10˚C, and 65MHz for ” Min ”, T
CC
CC
= 3.6V, R_FB = V
= 3.6V, R_FB = GND
Parameter
FIGURE 1. “Worst Case” Test Pattern
CC
4
(Continued)
A
A
= 70˚C,
= 70˚C,
f = 25
f = 25
f = 40
f = 65
MHz
MHz
MHz
MHz
−0.45
10.98
16.69
22.41
28.12
33.84
3.340
3.011
5.26
Min
2.5
0.5
2.5%/−5%
2.5%/−5%
2.5%/−5%
100kHz
100kHz
100kHz
11.43
17.14
22.86
28.57
34.29
5.71
Typ
0
±
±
±
20098604
+0.45
11.88
17.59
23.31
29.02
34.74
7.211
6.062
Max
6.16
100
10
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns