DS92LV1023TMSA National Semiconductor, DS92LV1023TMSA Datasheet
DS92LV1023TMSA
Specifications of DS92LV1023TMSA
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DS92LV1023TMSA Summary of contents
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... The DS92LV1023 was designed with the flow-through pinout and is available in a space saving 28–lead SSOP package. Block Diagrams TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation Features n 40–66 MHz Single 10:1 Serializer with 400–660 Mb/s throughput ...
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Block Diagrams (Continued) Functional Description The DS92LV1023 is a 10-bit Serializer device which together with a compatible deserializer (i.e. DS92LV1224) forms a chipset designed to transmit data over FR-4 printed circuit board backplanes and balanced copper cables at clock speeds ...
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Data Transfer (Continued) clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0–ROUT9 is invalid. The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the ...
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... Ordering Information NSID DS92LV1023TMSA DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DIN4 Held Low-DIN5 Held High Creates an RMT Pattern FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial Output www.national.com Function Serializer 10093324 DIN8 Held Low-DIN9 Held High Creates an RMT Pattern ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS/LVTTL Input Voltage −0. LVCMOS/LVTTL Output Voltage −0. Bus LVDS Driver Output Voltage Bus LVDS Output Short Circuit Duration ...
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Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Transmit Clock Period TCP t Transmit Clock High Time TCIH t Transmit Clock Low Time TCIL t TCLK Input Transition CLKT Time ...
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AC Timing Diagrams and Test Circuits FIGURE 2. “Worst Case” Serializer ICC Test Pattern FIGURE 3. Serializer Bus LVDS Output Load and Transition Times FIGURE 4. Serializer Input Clock Transition Time Timing shown for TCLK_R/F = LOW FIGURE 5. Serializer ...
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AC Timing Diagrams and Test Circuits FIGURE 6. Serializer TRI-STATE Test Circuit and Timing FIGURE 7. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays www.national.com (Continued) 10093309 8 10093310 ...
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AC Timing Diagrams and Test Circuits (Continued) FIGURE 8. SYNC Timing Delays FIGURE 9. Serializer Delay 9 10093323 10093311 www.national.com ...
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AC Timing Diagrams and Test Circuits + − (DO )–( Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. Application Information USING THE SERIALIZER AND DESERIALIZER CHIPSET The Serializer and Deserializer chipset is ...
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FIGURE 11. Random Lock Hot Insertion 11 10093317 www.national.com ...
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... I DGND I AVCC I AGND I www.national.com DS92LV1023TMSA - Serializer 10093318 No. 3–12 Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register. 13 Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects TCLK active edge for strobing of DIN data. High selects rising edge ...
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... Tel: 1-800-272-9959 Deutsch Tel: +49 (0) 69 9508 6208 English www.national.com Français Tel: +33 ( 8790 Order Number DS92LV1023TMSA NS Package Number MSA28 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...