DS90CF388VJD National Semiconductor, DS90CF388VJD Datasheet - Page 11

• Manufacturer Part Number: DS90CF388VJD
• Description: IC,Serial-to-Parallel Converter,CMOS,TQFP,100PIN
• Manufacturer: National Semiconductor

Specifications of DS90CF388VJD

• Number Of Elements: 8
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Output Type: Flat Panel Display
• Differential Output Voltage: 450mV
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Number Of Receivers: 8
• Number Of Drivers: 48
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Not Compliant

AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by RSPOS (receiver input strobe position) min and max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
See Applications Informations section for more details.
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
See Applications Informations section for more details.
j
j
j
j
j
j
Cable Skew — typically 10 ps to 40 ps per foot, media dependent
TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
d = Tppos — Transmitter output pulse position (min and max)
f = TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
m = extra margin - assigned to ISI in long cable applications
FIGURE 13. Receiver Skew Margin (RSKMD) with DESKEW
(Continued)
FIGURE 12. Receiver Skew Margin
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