DS90C365AMT National Semiconductor, DS90C365AMT Datasheet - Page 11

• Manufacturer Part Number: DS90C365AMT
• Manufacturer: National Semiconductor

Specifications of DS90C365AMT

• Number Of Elements: 3
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Flat Panel Display
• Differential Output Voltage: 450mV
• Transmission Data Rate: 612.5MBps
• Power Dissipation: 1.98W
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TSSOP
• Number Of Receivers: 21
• Number Of Drivers: 3
• Lead Free Status / RoHS Status: Not Compliant

Applications Information
The
DS90C365, DS90C363A, DS90C363 in TSSOP 48-lead
package, and it is a pin-for-pin replacements.
This device DS90C365A also features reduced variation of
the TCCD parameter which is important for dual pixel appli-
cations. (See AN-1084)
This device may also be used as a replacement for the
DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/modifica-
tions:
1.
2.
3.
TRANSMITTER INPUT PINS
The TxIN and control input pins are compatible with LVCMOS
and LVTTL levels. These pins are not 5V tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
Unlike
DS90C365A does not require any special requirement for se-
quencing of the input clock/data and PD (PowerDown) signal.
The DS90C365A offers a more robust input sequencing fea-
Pin Diagram for TSSOP Packages
Change 5V power supply to 3.3V. Provide this 3.3V
supply to the V
transmitter.
The DS90C365A transmitter input and control inputs
accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
To implement a falling edge device for the DS90C365A,
the R_FB pin may be tied to ground OR left unconnected
(an internal pull-down resistor biases this pin low).
Biasing this pin to Vcc implements a rising edge device.
DS90C365A
the
DS90C365,
CC
is
, LVDS V
backward
CC
DS90C(F)383A/363A,
and PLL V
compatible
CC
of the
with
DS90C365AMT
the
the
11
ture where the input clock/data can be inserted after the
release of the PD signal. In the case where the clock/data is
stopped and reapplied, such as changing video mode within
Graphics Controller, it is not necessary to cycle the PD signal.
However, there are in certain cases where the PD may need
to be asserted during these mode changes. In cases where
the source (Graphics Source) may be supplying an unstable
clock or spurious noisy clock output to the LVDS transmitter,
the LVDS Transmitter may attempt to lock onto this unstable
clock signal but is unable to do so due the instability or quality
of the clock source. The PD signal in these cases should then
be asserted once a stable clock is applied to the LVDS trans-
mitter. Asserting the PWR DOWN pin will effectively place the
device in reset and disable the PLL, enabling the LVDS
Transmitter into a power saving standby mode. However, it is
still generally a good practice to assert the PWR DOWN pin
or reset the LVDS transmitter whenever the clock/data is
stopped and reapplied but it is not mandatory for the
DS90C365A.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C365A can support Spread Spectrum Clocking sig-
nal type inputs. The DS90C365A outputs will accurately track
Spread Spectrum Clock/Data inputs with modulation frequen-
cies of up to 100kHz (max.)with either center spread of ±2.5%
or down spread -5% deviations.
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have V
V
separate de-coupling bypass capacitor groups. There is no
requirement on which VCC entering the device first.
CC
and PLL V
20100540
CC
from the same power source with three
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CC
, LVDS