XC3S500E-4CPG132C Xilinx Inc, XC3S500E-4CPG132C Datasheet - Page 76
![FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA](/photos/6/70/67095/pk373-cp132_sml.jpg)
XC3S500E-4CPG132C
Manufacturer Part Number
XC3S500E-4CPG132C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4CPG132C
Package
132CSBGA
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
92
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
92
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
132-TFBGA, CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1484
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4CPG132C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4CPG132C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Functional Description
available SPI Flash PROMs use different command proto-
cols. The FPGA’s variant select pins, VS[2:0], define how
the FPGA communicates with the SPI Flash, including
which SPI Flash command the FPGA issues to start the
read operation and the number of dummy bytes inserted
before the FPGA expects to receive valid data from the SPI
Flash.
expected to operate with Spartan-3E FPGAs. Other com-
patible devices might work but have not been tested for suit-
ability with Spartan-3E FPGAs. All other VS[2:0] values are
reserved for future use. Consult the data sheet for the
desired SPI Flash device to determine its suitability. The
basic timing requirements and waveforms are provided in
Serial Peripheral Interface (SPI) Configuration Timing
Module 3.
76
S
Figure 53: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B) Commands
Although SPI is a standard four-wire interface, various
Table 53
Recommend
open-drain
PROG_B
driver
shows the available SPI Flash PROMs
TMS
TDO
TCK
TDI
+2.5V
JTAG
Variant Select
SPI Mode
S
‘0’
‘0’
‘1’
‘1’
‘1’
P
HSWAP
M2
M1
M0
VS2
VS1
VS0
TDI
TMS
TCK
PROG_B
Spartan-3E
VCCINT
FPGA
+1.2V
GND
www.xilinx.com
in
VCCAUX
VCCO_0
VCCO_2
CSO_B
INIT_B
DONE
DOUT
CCLK
MOSI
TDO
DIN
Figure 53
SPI Flash PROMs that support the 0x03 READ command
or the 0x0B FAST READ commands.
Figure 54
DataFlash serial PROMs, which also use an SPI-based pro-
tocol. ‘B’-series DataFlash devices are limited to FPGA
applications operating over the commercial temperature
range. Industrial temperature range applications must use
‘C’- or ‘D’-series DataFlash devices, which have a shorter
DataFlash select setup time, because of the faster FPGA
CCLK frequency at cold temperatures.
Figure 57, page 84
FPGAs with different configurations, all stored in a single
SPI Flash. The diagram uses standard SPI Flash memories
but the same general technique applies for Atmel
DataFlash.
VCCO_0
+3.3V
+2.5V
shows the general connection diagram for those
shows the connection diagram for Atmel
demonstrates how to configure multiple
I
W
‘1’
DS312-2 (v3.8) August 26, 2009
P
+3.3V
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
+2.5V
Product Specification
+3.3V
GND
DS312-2_46_082009
VCC
Serial
Flash
SPI
R
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