HV257FG-G Supertex, HV257FG-G Datasheet - Page 7

• Manufacturer Part Number: HV257FG-G
• Description: Sample & Hold Amplifiers 32-Ch MEMS Drvr IC
• Manufacturer: Supertex

Specifications of HV257FG-G

• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Package / Case: MQFP-100
• Lead Free Status / RoHS Status: Compliant

RSINK / RSOURCE
The VDD_BYP, VDD_BYP, and VNN_BYP pins are internal,
high impedance current, mirror gate nodes, brought out to
mantain stable opamp biasing currents in noisy power supply
environments. 0.1uF/25V bypass capacitors, added from
VPP_BYP pin to VPP, from VDD_BYP pin to VDD, and from
Ground Isolation (AGND/DGND Isolation)
It is important that the AGND pin is connected to a clean
ground. The hold capacitors are internally connected to the
AGND, and any ground noise will directly couple to the high
voltage outputs (with a gain of 72). The analog and digital
Single star GND
BYP _ VNN Cap
BYP _ VPP Cap
BYP_ VDD Cap
0.1uF / 25V
0.1uF / 25V
0.1uF / 25V
DAC
C4
C2
DGND
DVDD
BYP _ VPP
BYP _ VNN
BYP_ VDD
C5
VDD
VNN
VPP
AVNN
A
DVNN
VSIG
GND
C6
C3
1 (pins 89, 43)
AVDD
EN, A
Sample
switch
Set by RSOURCE
To internal biasing
Set by RSINK
0
-A
4
C_hold
10pF
External bypass caps:
C1 = 0.1µF / 500V
C2, C3, C4, C5 = 0.1µF / 25V
7
VNN_BYP to VNN, will force the high impedance gate nodes
to follow fluctuation of power lines. The expected voltages at
the VDD_BYP, and VNN_BYP pins are typically 1.5 volts
from their respectful power supply. The expected voltage at
VPP_BYP is typically 3V below VPP.
ground traces on the PCB should be physically separated to
reduce digital switching noise degrading the signal to noise
performance.
LVOpamp
HVOpamp
C_comp
A
GND
Current limit
HV
Current limit
OUT
2 (pin 39)
HVOpamp
0
71R
1R
HVOpamp
VPP
C1
HV
OUT
HV
OUT
C_comp
31