ADRF6510ACPZ-WP Analog Devices Inc, ADRF6510ACPZ-WP Datasheet - Page 14

• Manufacturer Part Number: ADRF6510ACPZ-WP
• Manufacturer: Analog Devices Inc

Specifications of ADRF6510ACPZ-WP

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

ADRF6510
THEORY OF OPERATION
The ADRF6510 consists of a matched pair of buffered, program-
mable filters followed by variable gain amplifiers and output
ADC drivers. The block diagram of a single channel is shown
in Figure 41. The programmability of the bandwidth and of the
pre- and post-filtering gain offers great flexibility when coping
with signals of varying levels in the presence of noise and large,
undesired signals nearby. The entire differential signal chain is
dc-coupled with flexible interfaces at the input and output. The
bandwidth and gain setting controls for the two channels are
shared, ensuring close matching of their magnitude and phase
responses. The ADRF6510 can be fully disabled through the
ENBL pin.
Filtering and amplification are fundamental operations in any
signal processing system. Filtering is necessary to select the
intended signal while rejecting out-of-band noise and interferers.
Amplification increases the level of the desired signal to overcome
noise added by the system. When used together, filtering and
amplification can extract a low level signal of interest in the
presence of noise and out-of-band interferers. Such analog
signal processing alleviates the requirements on the analog,
mixed signal, and digital components that follow.
INPUT BUFFERS
The input buffers provide a convenient interface to the sensitive
filter sections that follow. They set a differential input impedance
of 400 Ω and sit at a nominal common-mode voltage of VPS/2.
The inputs can be dc-coupled or ac-coupled. If using direct
dc-coupling, the common-mode voltage, V
1.5 V to 3 V. A current flows into or out of the input pins to
accommodate the difference in common-mode voltages. The
current into each pin is given by
The input buffers in both channels can be configured simulta-
neously to a gain of 6 dB or 12 dB through the GNSW pin. When
configured for a 6 dB gain, the buffers support up to a 1 V p-p
differential input level with >50 dBc harmonic distortion. For
a 12 dB gain setting, the buffers support 0.5 V p-p inputs.
PROGRAMMABLE FILTERS
The integrated programmable filter is the key signal processing
function in the ADRF6510. The filters follow a six-pole Butter-
worth prototype response that provides a compromise between
BASEBAND
Figure 41. Signal Path Block Diagram for a Single Channel of the ADRF6510
INPUTS
(V
CM
GAIN SWITCH
– (VPS/2))/200 Ω
PREAMP
6dB/12dB
PREAMP
PROGRAMMING
INTERFACE
SPI BUS
1MHz TO 30MHz
PROG. FILTERS
FILTER
SPI
GAIN CONTROL
ANALOG
30mV/dB
50dB
VGA
CM
OUTPUT ADC
, can range from
DRIVER
COMMON-MODE
CONTROL
OUTPUT
BASEBAND
OUTPUTS
Rev. 0 | Page 14 of 28
band rejection, ripple, and group delay. The 0.5 dB bandwidth is
programmed from 1 MHz to 30 MHz in 1 MHz steps via the serial
programming interface (SPI) as described in the Programming
the Filters section.
The filters are designed so that the Butterworth prototype filter
shape and group delay responses vs. frequency are retained for
any bandwidth setting. Figure 42 and Figure 43 illustrate the
ideal six-pole Butterworth gain and group delay responses,
respectively. The group delay, τ
where:
φ is the phase in radians.
ω = 2πf is the frequency in radians/second.
Note that for a frequency scaled filter prototype, the absolute
magnitude of the group delay scales inversely with the band-
width; however, the shape is retained. For example, the peak
group delay for a 28 MHz bandwidth setting is 14× less than
for a 2 MHz setting.
Figure 42. Sixth-Order Butterworth Magnitude Response for 0.5 dB
τ
–100
–120
–140
–160
–180
–100
Bandwidths; Programmed from 2 MHz to 29 MHz in 1 MHz Steps
g
–20
–40
–60
–80
500
400
300
200
100
Figure 43. Sixth-Order Butterworth Group Delay Response for
= −∂φ/∂ω
100k
0
0
1M
0.5 dB Bandwidths; Programmed to 2 MHz and 28 MHz
10M
1M
2MHz
FREQUENCY (Hz)
FREQUENCY (Hz)
g
, is defined as
100M
10M
28MHz
14x
100M
1G