AD9858BSV Analog Devices Inc, AD9858BSV Datasheet - Page 8

• Manufacturer Part Number: AD9858BSV
• Manufacturer: Analog Devices Inc

Specifications of AD9858BSV

• Lead Free Status / RoHS Status: Not Compliant

AD9858
Pin No.
17
18
19
22
29, 30, 37 to 39,
41, 42, 49, 50, 52,
69, 74, 80, 85, 87, 88
31, 32, 35, 36,
40, 43, 44, 47,
48, 51, 70, 73,
77, 86, 89, 90
33
34
45
46
53
54
55
56
57
58
59, 60, 75, 76
61
62, 67
63, 68
64
65, 66
71
72
78
79
81, 82
83, 84
91
92
97, 98
99
100
Mnemonic
SDO
SDIO
WR/SCLK
RD/CS
AGND
AVDD
REFCLK
REFCLK
LO
LO
RF
RF
IF
IF
PFD
PFD
NC
CPISET
CPVDD
CPGND
CPFL
CP
DIV
DIV
DACBP
DACISET
IOUT
IOUT
SPSELECT
RESET
PS0, PS1
FUD
SYNCLK
EPAD
I/O
O
I/O
I
I
I
I
I
I
I
I
I
I
O
O
I
I
I
I
I
O
O
I
I
I
O
O
I
I
I
I
O
Description
This is valid for serial programming mode only. When operating the I/O port as a 3-wire
serial port, this pin serves as a unidirectional serial data output pin. When operated as a 2-wire
serial port, this pin is unused.
This is valid for serial programming mode only. When operating the I/O port as a 3-wire serial
port, this pin is the serial data input. When operated as a 2-wire serial port, this pin is the
bidirectional serial data pin.
When the I/O port is configured for parallel programming mode, this pin functions as an active
low write pulse (WR). When configured for serial programming mode, this pin functions as the
serial data clock (SCLK).
When the I/O port is configured for parallel programming mode, this pin functions as an active
low read pulse (RD). When configured for serial programming mode, this pin functions as an
active low chip select (CS) that allows multiple devices to share the serial bus.
Analog Ground.
Analog Supply Voltage.
Reference Clock Complementary Input. When the REFCLK port operates in single-ended mode,
REFCLK should be decoupled to AVDD with a 0.1 μF capacitor.
Reference Clock Input.
Mixer Local Oscillator (LO) Complementary Input. When the LO port operates in single-ended
mode, LO should be decoupled to AVDD with a 0.1 μF capacitor.
Mixer Local Oscillator (LO) Input.
Analog Mixer RF Complementary Input. When the RF port operates in single-ended mode,
RF should be decoupled to AVDD with a 0.1 μF capacitor.
Analog Mixer RF Input.
Analog Mixer IF Output.
Analog Mixer IF Complementary Output.
Phase Frequency Detector Complementary Input. When the PFD port operates in single-ended
mode, PFD should be decoupled to AVDD with a 0.1 μF capacitor.
Phase Frequency Detector Input.
No Connection.
Charge Pump Output Current Control. A resistor connected from CPISET to CPGND establishes
the reference current for the charge pump.
Charge Pump Supply Voltage.
Charge Pump Ground.
Charge Pump Fast Lock Output.
Charge Pump Output.
Phase Frequency Detector Feedback Input.
Phase Frequency Detector Feedback Complementary Input. When the DIV port operates in
single-ended mode, DIV should be decoupled to AVDD with a 0.1 μF capacitor.
DAC Baseline Decoupling Pin. Typically bypassed to Pin 77 with a 0.1 μF capacitor.
A resistor connected from DACISET to AGND establishes the reference current for the DAC.
DAC Output.
DAC Complementary Output.
I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0 is serial programming mode, and
Logic 1 is parallel programming mode.
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default
operating conditions.
Used to select one of the four internal profiles. These pins are synchronous to the SYNCLK output.
Frequency Update. The rising edge transfers the contents of the internal buffer registers to the
memory registers. This pin is synchronous to the SYNCLK output.
Clock Output Pin. Serves as a synchronizer for external hardware. SYNCLK runs at REFCLK/8.
Exposed paddle must be soldered to ground.
Rev. C | Page 8 of 32