AD9852ASQ Analog Devices Inc, AD9852ASQ Datasheet - Page 36

• Manufacturer Part Number: AD9852ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9852ASQ

• Lead Free Status / RoHS Status: Not Compliant

AD9852
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Table 11.
Pin
SCLK
CS
SDIO
SDO
I/O RESET
Notes on Serial Port Operation
The AD9852 serial port configuration bits reside in Bit 1 and
Bit 0 of Register Address 20 hex. The configuration changes
immediately upon a valid I/O update. For multibyte transfers,
writing this register can occur during the middle of a
communication cycle. Care must be taken to compensate for
this new configuration for the remainder of the current
communication cycle.
The system must maintain synchronization with the AD9852,
or the internal control logic is not able to recognize further
instructions. For example, if the system sends the instruction to
write a 2-byte register and then pulses the SCLK pin for a 3-byte
register (24 additional SCLK rising edges), communication
synchronization is lost. In this case, the first 16 SCLK rising
edges after the instruction cycle properly write the first two data
bytes into the AD9852, but the next eight rising SCLK edges are
interpreted as the next instruction byte, not the final byte of the
previous communication cycle.
In cases where synchronization is lost between the system and
the AD9852, the I/O RESET pin provides a means to re-establish
synchronization without reinitializing the entire chip. Asserting
the I/O RESET pin (active high) resets the AD9852 serial port
state machine, terminating the current I/O operation and putting
the device into a state where the next eight SCLK rising edges
are understood to be an instruction byte. The I/O RESET pin
must be deasserted (low) before the next instruction byte write
can begin. Any information written to the AD9852 registers
during a valid communication cycle prior to loss of synchro-
nization, remains intact.
Description
Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state
machines. SCLK maximum frequency is 10 MHz.
Chip Select (Pin 22). Active low input that allows more than one device on the same serial communication line. The SDO and
SDIO pins go to a high impedance state when this input is high. If driven high during a communication cycle, that cycle is
suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK.
Serial Data I/O (Pin 19). Data is always written into the AD9852 on this pin. However, this pin can be used as a bidirectional data
line. The configuration of this pin is controlled by Bit 0 of Register Address 20 hex. The default is Logic 0, which configures the
SDIO pin as bidirectional.
Serial Data Out (Pin 18). Data is read from this pin for protocols that use separate lines for transmitting and receiving data.
In the case where the AD9852 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high
impedance state.
Synchronize I/O Port (Pin 17). Synchronizes the I/O port state machines without affecting the contents of the addressable
registers. An active high input on the I/O RESET pin causes the current communication cycle to terminate. After I/O RESET
returns low (Logic 0), another communication cycle may begin, starting with the instruction byte.
Rev. D | Page 36 of 52
MSB/LSB TRANSFERS
The AD9852 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 1 of Serial Bank 20 hex. When
this bit is set active high, the AD9852 serial port is in LSB-first
format. This bit defaults low, to the MSB-first format. The
instruction byte must be written in the format indicated by Bit 1
of Serial Register Bank 20 hex, that is, if the AD9852 is in LSB-
first mode, the instruction byte must be written from least
significant bit to most significant bit.
SCLK
SDIO
SCLK
SDIO
SDO
CS
CS
SYMBOL
T
T
T
T
T
T
PRE
SCLK
DSU
SCLKPWH
SCLKPWL
DHLD
Figure 53. Timing Diagram for Data Write to AD9852
T
T
Figure 54. Timing Diagram for Read from AD9852
PRE
DSU
FIRST BIT
SYMBOL
T
DV
T
SCLKPWH
MIN
30ns
100ns
30ns
40ns
40ns
0ns
FIRST BIT
T
DHLD
T
SCLK
DEFINITION
CS SETUP TIME
PERIOD OF SERIAL DATA CLOCK
SERIAL DATA SETUP TIME
SERIAL DATA CLOCK PULSE WIDTH HIGH
SERIAL DATA CLOCK PULSE WIDTH LOW
SERIAL DATA HOLD TIME
MAX
30ns
T
T
SCLKPWL
DV
DEFINITION
DATA VALID TIME
SECOND BIT
SECOND BIT