PF38F2030W0YTQ1 Micron Technology Inc, PF38F2030W0YTQ1 Datasheet - Page 14
PF38F2030W0YTQ1
Manufacturer Part Number
PF38F2030W0YTQ1
Description
Manufacturer
Micron Technology Inc
Datasheet
1.PF38F2030W0YTQ1.pdf
(52 pages)
Specifications of PF38F2030W0YTQ1
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Intel® Wireless Flash Memory (W18/W30 SCSP)
4.2
Table 1.
June 2005
14
F[3:1]-CE#
P[2:1]-CS#
Symbol
S-CS1#
D[15:0]
A[21:0]
S-CS2
ADV#
WAIT
CLK
Output
Output
Input/
Type
Input
Input
Input
Input
Input
Input
Signal Descriptions
Table 1
Signal Descriptions (Sheet 1 of 2)
WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for
information on how to use this signal in asynchronous-read mode.
FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted,
standby levels.
S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die.
PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers,
decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power
is reduced to standby levels.
P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This
ball is RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available
only on SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without
PSRAM or with a single PSRAM.
describes active signals used on the 32WQ and 64WQ W18/W30 SCSP family.
ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are
internally latched during write operations.
A0 is the lowest-order word address.
A[25:22] denote high-order addresses reserved for future device densities
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read
cycles. Data signals float when the device or its outputs are deselected. Data are internally latched
during writes.
FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in
synchronous-read mode. During synchronous read operations, the initial address is latched on the
rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first.
CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for
information on how to use this signal in asynchronous-read mode.
FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is
latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever
occurs first.
Refer to the flash discrete product datasheet for information on how to use this signal in
asynchronous-read mode.
FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0].
WAIT is High-Z whenever the flash die is deselected (CE# = V
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted,
the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are
placed in High-Z.
F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one
flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash
die.
SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic,
input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are
deasserted (S-CS1# = V
• 4-Mbit: A[17:0]
• 8-Mbit: A[18:0]
• 16-Mbit: A[19:0]
• 32-Mbit: A[20:0]
• 64-Mbit: A[21:0]
Intel® Wireless Flash Memory (W18/W30 SCSP)
Order Number: 251407, Revision: 009
IH
and/or S-CS2 = V
Name and Function
IL
), the SRAM is deselected and its power is reduced to
IL
). WAIT is not gated by OE#.
Datasheet