RD38F2030W0ZBQ1 Micron Technology Inc, RD38F2030W0ZBQ1 Datasheet - Page 32

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RD38F2030W0ZBQ1

Manufacturer Part Number
RD38F2030W0ZBQ1
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of RD38F2030W0ZBQ1

Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

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TI
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Manufacturer:
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Intel® Wireless Flash Memory (W18/W30 SCSP)
Table 2.
Table 3.
June 2005
32
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Read
Write
Output
Disable
Standby
Data
Retention
Sync
Array
Read
All Async/
Sync
Non-array
Read
Write
Output
Disable
Standby
Reset
Mode
Mode
For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the
memory bus.
WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted.
For flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so, F[2:1]-OE# will
override F-WE#.
For SRAM, R-OE# and R-WE# should never be asserted simultaneously.
X can be V
Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
Refer to W18 and W30 datasheet for valid D
The SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2.
The SRAM can be placed into data retention mode by lowering S-VCC to the V
Flash + SRAM Bus Operations
Flash + PSRAM Bus Operations
IL
H
H
H
H
H
L
or V
IH
H
L
L
L
L
X
Flash must be in High-Z
Any flash mode allowed
for inputs, V
Intel® Wireless Flash Memory (W18/W30 SCSP)
H
H
X
X
L
L
Order Number: 251407, Revision: 009
PPL
H
H
H
X
X
L
, V
PPH
L
X
X
X
X
X
or V
IN
V
V
PPLK
during flash writes.
PPH
PPL
or
X
X
X
X
X
for F-VPP.
Active
Asserted
Asserted
Active
High-Z
High-Z
H
X
L
L
L
Any PSRAM mode allowed
PSRAM must be in High-Z
Same as SRAM standby
H
H
H
X
L
DR
H
L
X
X
limit when in standby mode.
H
H
X
L
L
L
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
SRAM
D
Flash
D
Flash
D
Flash
Flash
Flash
Flash
D
D
OUT
OUT
OUT
IN
IN
Datasheet
1, 4, 8, 2
4, 5, 8, 2
5, 2
5, 8, 2
9, 2
1, 2, 3, 4, 6
1, 2, 3, 4, 6, 7
3, 4, 6, 8
6
6
6

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