LRS1806C Sharp Electronics, LRS1806C Datasheet - Page 31
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LRS1806C
Manufacturer Part Number
LRS1806C
Description
Manufacturer
Sharp Electronics
Datasheet
1.LRS1806C.pdf
(58 pages)
Specifications of LRS1806C
Lead Free Status / RoHS Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LRS1806C
Manufacturer:
Sharp
Quantity:
191
sharp
13.3 Write Cycle
Notes:
Symbol
1. Writing data into lower byte (S-WE controlled)
2. Witing data into lower byte (S-LB controlled)
3. Writing data into upper byte (S-WE controlled)
4. Writing data into upper byte (S-UB controlled)
5. Writing data into both byte (S-WE controlled)
6. Writing data into both byte (S-LB, S-UB controlled)
7. Read or write with using both S-LB and S-UB, the timing edge of S-LB and S-UB must be same.
8. While DQ pins are in the output state, the data that is opposite to the output data should not be given.
t
t
t
t
t
t
t
t
t
t
t
WHZ
AHC
t
t
ASC
t
C1H
WC
CW
AW
BW
WR
DW
OW
WP
DH
AS
1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE
2) The data on lower byte are latched up into the memory cell during S-WE = Low and S-LB = Low.
1) Data can be written by adding Low pulse into S-LB when the address is set while holding S-CE
2) The data on lower byte are latched up into memory cell during S-WE = Low and S-LB = Low.
1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE
2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low.
1) Data can be written by adding Low pulse S-UB when the address is set while holding S-CE
2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low.
1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE
2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low.
1) Data can be written by adding Low pulse into S-LB and S-UB when the address is set while holding S-CE
2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low
S-CE
S-CE
S-CE
S-CE
S-CE
S-CE
Write Cycle Time
Chip Enable to End of Write
Address Setup to S-CE
Address Hold to S-CE
S-CE
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Byte Select Time
Write Recovery Time
Input Data Setup Time
Input Data Hold Time
S-WE High to Output Active
S-WE Low to Output in High-Z
2
2
2
2
2
2
1
= High, S-LB = Low and S-UB = High.
= High, S-UB = High and S-WE = Low.
= High, S-LB = High and S-UB = Low.
= High, S-LB = High and S-WE = Low.
= High, S-LB = Low and S-UB = Low.
= High and S-WE = Low.
(1,2,3,4,5,6,7,8)
High Pulse Width
1
1
High
Low
Parameter
L R S1 8 3 6
(T
A
= -30°C to +85°C, S-V
Notes
Min.
85
70
30
70
50
70
35
0
0
0
0
0
5
1
= Low,
1
1
1
1
= Low,
= Low,
= Low,
32,000
= Low,
CC
Max.
30
= 2.7V to 3.1V)
1
= Low,
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28