IS42S16400C1-7T-TR ISSI, Integrated Silicon Solution Inc, IS42S16400C1-7T-TR Datasheet - Page 15

• Manufacturer Part Number: IS42S16400C1-7T-TR
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400C1-7T-TR

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 100mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

IS42S16400C1
FUNCTIONAL DESCRIPTION
The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank
DRAMs which operate at 3.3V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks
is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0-A11
select the row). The address bits (A0-A7) registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
10/25/05
1-800-379-4774
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 64M SDRAM is initialized after the power is applied
to V
with DQM High and CKE High.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 100µs period and
continue should at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100µs delay has been satisfied. All banks
must be precharged. This will leave all banks in an idle
state, after which at least two AUTO REFRESH cycles must
be performed. After the AUTO REFRESH cycles are com-
plete, the SDRAM is then ready for mode register program-
ming.
The mode register should be loaded prior to applying any
operational command because it will power up in an
unknown state. After the Load Mode Register command, at
least two NOP commands must be asserted prior to any
command.
DD
and V
DDQ
(simultaneously), and the clock is stable
ISSI
15
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