W9825G6DH75I Winbond, W9825G6DH75I Datasheet
W9825G6DH75I
Specifications of W9825G6DH75I
Related parts for W9825G6DH75I
W9825G6DH75I Summary of contents
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... Power Down Mode ....................................................................................................... 11 7.18 No Operation Command............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode.................................................................................................... 11 8. OPERATION MODE ................................................................................................................. 12 9. ELECTRICAL CHARACTERISTICS......................................................................................... 13 9.1 Absolute Maximum Ratings .......................................................................................... 13 9.2 Recommended DC Operating Conditions .................................................................... 13 4M × 4 BANKS × 16 BITS SDRAM Publication Release Date: Apr. 24, 2008 - 1 - W9825G6DH Revision A12 ...
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Capacitance .................................................................................................................. 13 9.4 DC Characteristics ........................................................................................................ 14 9.5 AC Characteristics and Operating Condition................................................................ 15 10. TIMING WAVEFORMS ............................................................................................................. 18 10.1 Command Input Timing ................................................................................................ 18 10.2 Read Timing.................................................................................................................. 19 10.3 Control Timing of Input/Output Data ............................................................................. 20 10.4 ...
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... The -75/75I is compliant to the 133MHz/CL3 specification (the 75I grade which is guaranteed to support -40°C ~ 85°C). Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length full page when a bank and row is selected by an ACTIVE command ...
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... AVAILABLE PART NUMBER PART NUMBER W9825G6DH-6 W9825G6DH-6C W9825G6DH-6I W9825G6DH-75 W9825G6DH75I 4. PIN CONFIGURATION DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQM W E CAS RAS CS BS0 BS1 A10/ SPEED SELF REFRESH GRADE CURRENT (MAX) 166MHz/CL3 or 3mA 133MHz/CL2 166MHz/CL3 3mA 166MHz/CL3 3mA 133MHz/CL3 ...
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... CS 18 RAS 17 CAS 16 WE LDQM, 15, 39 UDQM 38 CLK 37 CKE 1, 14 Power (+3.3V) Power for input buffers and logic circuit inside DRAM. CC 28, 41 Power (+3.3V 43 CCQ 6, 12, 46 SSQ Connection FUNCTION Multiplexed pins for row and column address. Address Row address: A0−A12. Column address: A0−A8. ...
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BLOCK DIAGRAM CLK CLO CK BUFFER CKE CS CO NTRO L SIG NAL G ENERATO R RAS CO MMAND CAS DECO DER W E A10 MO DE REG IST ER A0 ADDRESS BUFFER A9 A11 A12 BS0 BS1 REFRESH ...
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... The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t ) ...
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Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address ...
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Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table ...
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... Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high ...
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... CKE held high for a period equal to t 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations Operation Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of the clock ...
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OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1) , (2)) DEICE COMMAND STATE Bank ...
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ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER Input, Output Voltage Supply Voltage Operating Temperature(-6/-6C/-75) Operating Temperature(-6I/75I) Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings ...
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DC Characteristics = 3.3V ± 0.3V 70°C for –6/-6C/-75 PARAMETER Operating Current min., = min Bank Operation Active precharge command cycling without burst operation Standby ...
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AC Characteristics and Operating Condition ± (VCC = 3.3V 0.3V 70°C for -6/-6C/-75 PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b) ...
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PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time CLK Cycle Time CLK High ...
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Notes: 1. Operation exceeds "Absolute Maximum Ratings" may cause permanent damage to the devices. 2. All voltages are referenced These parameters depend on the cycle rate and listed values are measured at a cycle rate with the ...
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TIMING WAVEFORMS 10.1 Command Input Timing Command Input Timing CLK RAS CAS WE A0-A12 BS0 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS ...
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Read Timing CLK CS RAS CAS A12 BS0 Read Command Read CAS Latency Valid Data-Out Publication Release Date:Apr. 24, 2008 - 19 - W9825G6DH ...
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Control Timing of Input/Output Data Input Data (Word Mask) CLK t CMH DQM Valid Data-in DQ0 -15 (Clock Mask) CLK t CKH CKE Valid DQ0 -15 Data-in Output Data (Output Enable) ...
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Mode Register Set Cycle CLK t t CMS CMH CMS CMH RAS t t CMS CMH CAS t t CMS CMH A0-A12 Register set data BS0 Burst Length A2 ...
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OPERATING TIMING EXAMPLE 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = CLK RAS t RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9, RAa CAw ...
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Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge CLK CS RAS t RAS CAS WE BS0 BS1 t RCD A10 RAa RBb A0-A9, RAa CAw RBb A11, A12 DQM CKE ...
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Interleaved Bank Read (Burst Length = 8, CAS Latency = CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9, RAa CAx A11,A12 DQM CKE DQ t RRD Read Active Bank ...
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Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9, CAx RAa A11,A12 DQM CKE t CAC DQ t ...
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Interleaved Bank Write (Burst Length = CLK CS RAS CAS t RCD WE BS0 BS1 A10 RAa A0-A9, CAx RAa A11,A12 DQM CKE DQ ax0 ax1 t RRD Active Write Bank #0 ...
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Interleaved Bank Write (Burst Length = 8, Auto-precharge CLK CS RAS CAS WE BS0 BS1 t RCD RAa A10 A0-A9 CAx RAa A11,A12 DQM CKE DQ ax0 ax1 t RRD Active Write Bank ...
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Page Mode Read (Burst Length = 4, CAS Latency = CLK CS RAS CAS WE BS0 BS1 t t RCD RCD RAa RBb A10 A0-A9, RAa RBb CAI A11,A12 DQM CKE t ...
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Page Mode Read / Write (Burst Length = 8, CAS Latency = CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9, RAa CAx A11,A12 DQM CKE Bank ...
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Auto-precharge Read (Burst Length = 4, CAS Latency = CLK CS RAS t RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9, RAa CAw A11,A12 DQM CKE Bank ...
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Auto-precharge Write (Burst Length = CLK CS RAS t RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9, RAa CAw A11,A12 DQM CKE aw1 aw2 DQ aw0 Active Bank #0 Write ...
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Auto Refresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9, A11,A12 DQM CKE DQ All Banks Auto Prechage Refresh ...
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Self Refresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9, A11,A12 DQM t SB CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz ...
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Burst Read and Single Write (Burst Length = 4, CAS Latency = CLK CS RAS CAS t RCD WE BS0 BS1 A10 RBa A0-A9, RBa CBv A11,A12 DQM CKE DQ Read Active Bank ...
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Power Down Mode CLK CS RAS CAS WE BS A10 RAa A0-A9 RAa A11,A12 DQM t SB CKE t t CKS CKS DQ Active NOP Active Standby Power Down mode Note: The PowerDown ...
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Auto-precharge Timing (Read Cycle (1) CAS Latency burst length = 1 Command Read burst length = 2 Read Command burst length = 4 Read Command ...
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Auto-precharge Timing (Write Cycle (1) CAS Latency = 2 (a) burst length = 1 Write Command tWR DQ D0 (b) burst length = 2 Write Command (c) burst length = 4 Write Command DQ ...
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Timing Chart of Read to Write Cycle In the case of Burst Length = 4 (1) CAS Latency Command DQM Command DQM DQ (2) CAS Latency Command DQM DQ ...
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Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 (1) Read cycle ( a ) CAS latency =2 Read Command )CAS latency = 3 Read Command DQ (2) Write cycle Write Command Q0 DQ 11.20 ...
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CKE/DQM Input Timing (Write Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM ...
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CKE/DQM Input Timing (Read Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM ...
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PACKAGE SPECIFICATION 12.1 54L TSOP II - 400 mil Controlling Dimension: Millimeters SYM SEATING PLANE DIMENSION ...
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REVISION HISTORY VERSION DATE P0 Feb., 2006 A0 Aug., 2006 A1 Oct., 2006 A2 Jan, 2007 3,13,14,15 A3 Jan, 2007 3,13,14,15 A4 Feb. 15, 2007 A5 Apr. 25, 2007 A6 May 16, 2007 A7 Jun. 13, 2007 3,13,14,15, A8 ...
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... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales ...